Patents by Inventor Hiroshi Sunamura

Hiroshi Sunamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8003969
    Abstract: Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in contact with ion conducting part 4 and third electrode 3 formed at a second gap away from ion conducting part 4. Second electrode 2 supplies metal ions to the ion conductor, or receives the metal ions from the ion conductor to precipitate metal corresponding to the metal ions.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: August 23, 2011
    Assignee: NEC Corporation
    Inventors: Hisao Kawaura, Hiroshi Sunamura
  • Publication number: 20110198709
    Abstract: A semiconductor device includes a gate stack structure. The gate stack structure includes an interfacial layer formed on a semiconductor substrate, a high-k dielectric formed on the interfacial layer, a silicide gate including a diffusive material and an impurity metal, and formed over the high-k dielectric, and a barrier metal with a barrier effect to the diffusive material, and formed between the high-k dielectric and the metal gate. The impurity metal has a barrier effect to the diffusive material so that the diffusive material in the silicide gate can be prevented from being introduced into the high-k dielectric.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 18, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi Sunamura
  • Patent number: 7989924
    Abstract: A switching element with a switching voltage set higher than conventional, which includes an ion conduction layer including tantalum oxide, a first electrode provided in contact with the ion conduction layer, and a second electrode provided in contact with the ion conduction layer and capable of supplying the ion conduction layer with metal ions.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: August 2, 2011
    Assignee: NEC Corporation
    Inventors: Toshitsugu Sakamoto, Noriyuki Iguchi, Hiroshi Sunamura
  • Patent number: 7880215
    Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: February 1, 2011
    Assignee: NEC Corporation
    Inventors: Hirohito Watanabe, Motofumi Saitou, Hiroshi Sunamura
  • Patent number: 7821823
    Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hiroshi Sunamura, Kouji Masuzaki, Masayuki Terai
  • Patent number: 7804085
    Abstract: The switching element of the present invention is of a configuration that includes: a first electrode (14) and a second electrode (15) provided separated by a prescribed distance; a solid electrolyte layer (16) provided in contact with the first electrode (14) and the second electrode (15); a third electrode (18) that can supply metal ions and that is provided in contact with the solid electrolyte layer (16); and a metal diffusion prevention film (17) that covers points of the surface of the solid electrolyte layer (16) that are not in contact with the first electrode (14), the second electrode (15) or the third electrode (18). This configuration prevents the adverse effect of metal ions upon other elements.
    Type: Grant
    Filed: January 16, 2006
    Date of Patent: September 28, 2010
    Assignee: NEC Corporation
    Inventors: Hiroshi Sunamura, Naoya Inoue, Toshitsugu Sakamoto, Hisao Kawaura
  • Patent number: 7750332
    Abstract: The present invention provides a solid electrolyte switching device, which can maintain an on or off state when the power source is removed, the resistance of which in on the state is low, and which is capable of integration and re-programming, and FPGA and a memory device using the same, and a method of manufacturing the same.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: July 6, 2010
    Assignees: Japan Science and Technology Agency, Riken, NEC Corporation
    Inventors: Toshitsugu Sakamoto, Masakazu Aono, Tsuyoshi Hasegawa, Tomonobu Nakayama, Hiroshi Sunamura, Hisao Kawaura, Naohiko Sugibayashi
  • Publication number: 20100084716
    Abstract: Provided is a semiconductor device including a substrate, a gate insulating film which is formed on the substrate, and a gate electrode which is provided on the gate insulating film. The gate electrode includes a first metal silicide including a first metal material, and a second metal silicide including one of a second metal material and the second metal material in a contact portion between the gate insulating film and the gate electrode. The second metal silicide including the second metal material is a metal-rich silicide in which the composition ratio of the second metal material to silicon in the second metal silicide including the second metal is greater than 1.
    Type: Application
    Filed: October 1, 2009
    Publication date: April 8, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Hiroshi SUNAMURA, Kouji MASUZAKI
  • Publication number: 20100059730
    Abstract: To use a resistance change element having an MIM structure, which is obtained by stacking a metal, a metal oxide, and a metal, as a switching element, it is necessary to achieve OFF resistance higher than that required in a memory element by a factor of at least 1000. On the other hand, when a resistance change element is used as a memory element and when the difference between the ON resistance and the OFF resistance is a large value, high performance, for example, a short readout time, can be achieved. The present invention therefore provides a resistance change element capable of maintaining low ON resistance and achieving high OFF resistance. High OFF resistance can be achieved while low ON resistance is maintained by adding a second metal that is not contained in a metal oxide, which is a resistance change material, the second metal being capable of charge-compensating for metal deficiency or oxygen deficiency.
    Type: Application
    Filed: March 21, 2008
    Publication date: March 11, 2010
    Inventors: Kimihiko Ito, Hiroshi Sunamura, Yuko Yabe
  • Publication number: 20100044775
    Abstract: Provided is a semiconductor memory device that can retain information by trapping electric charges into a trap level in a gate insulating film. The information retention capacity is improved by restricting lateral diffusion of electric charges. The semiconductor memory device is provided with a semiconductor substrate (11), first and second impurities diffusion layers (12; 13) disposed in the semiconductor substrate, a gate insulating film (15) disposed on the semiconductor substrate, and a first gate electrode (16) disposed on the semiconductor substrate by way of the gate insulating film (15). The gate insulating film (15) has a silicon oxide film (14) that contains impurities which tend to combine with oxygen in the silicon oxide film and which are discrete at an atomic level.
    Type: Application
    Filed: December 7, 2007
    Publication date: February 25, 2010
    Inventor: Hiroshi Sunamura
  • Publication number: 20090316484
    Abstract: Disclosed is a semiconductor storage device comprising a semiconductor substrate, a first and a second impurity diffusion layer formed in the semiconductor substrate, a gate insulating film formed on the semiconductor substrate, and a first gate electrode formed on the semiconductor substrate via the gate insulating film. The gate insulating film has a nitrogen-containing silicon oxide film inside, and a silicon oxide film is so arranged on both sides of the nitrogen-containing silicon oxide film as to sandwich the nitrogen-containing silicon oxide film. In addition, the nitrogen composition in the nitrogen-containing silicon oxide film is increased from the semiconductor substrate side to the first gate electrode side.
    Type: Application
    Filed: December 1, 2006
    Publication date: December 24, 2009
    Inventors: Hiroshi Sunamura, Kouji Masuzaki, Masayuki Terai
  • Patent number: 7586215
    Abstract: When a predetermined voltage is applied between electrodes (302), metal ions deposit in a solid electrolyte (308), and thereby a conduction channel (310) is formed therein. The solid electrolyte switch (300) is thus turned on. Because this deposition mechanism is reversible, application of reverse voltage between the electrodes of the solid electrolyte switch (300) already turned on makes the deposited metal atoms to migrate in the solid electrolyte to thereby thin the conduction channel 300, thereby the channel finally disappears, and the solid electrolyte switch (300) is turned into a non-conductive state. Use of this switch successfully realizes an IC tag which can automatically be nullified without artificial nullification.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: September 8, 2009
    Assignee: NEC Corporation
    Inventors: Wataru Hattori, Hiroo Hongo, Fumiyuki Nihei, Hiroshi Sunamura
  • Publication number: 20090020742
    Abstract: The switching element of the present invention is of a configuration that includes: a first electrode (14) and a second electrode (15) provided separated by a prescribed distance; a solid electrolyte layer (16) provided in contact with the first electrode (14) and the second electrode (15); a third electrode (18) that can supply metal ions and that is provided in contact with the solid electrolyte layer (16); and a metal diffusion prevention film (17) that covers points of the surface of the solid electrolyte layer (16) that are not in contact with the first electrode (14), the second electrode (15) or the third electrode (18). This configuration prevents the adverse effect of metal ions upon other elements.
    Type: Application
    Filed: January 16, 2006
    Publication date: January 22, 2009
    Applicant: NEC CORPORATION
    Inventors: Hiroshi Sunamura, Naoya Inoue, Toshitsugu Sakamoto, Hisao Kawaura
  • Publication number: 20080144377
    Abstract: A diffusion layer (102) is formed in the surface region of a semiconductor substrate (101). A control gate electrode (103) is formed on the substrate. An interlayer dielectric film (108) covers the entire surface of the substrate. A drain leader line (104) made of a semiconductor such as n-type polysilicon is led from the drain region, and a source leader line (107) is led from the source region through the interlayer dielectric film. The drain leader line is surrounded by an annular floating gate (105). In erase, for example, the control gate is set to a ground potential, and a positive voltage is applied to the drain leader line to remove electrons in the floating gate to the drain leader line. In write, positive voltages are applied to the control gate electrode and drain leader line to generate CHE and inject hot electrons into the floating gate. This allows to thin the gate insulating film of a flash memory, increase the degree of integration of a nonvolatile memory, and lower the driving voltage.
    Type: Application
    Filed: November 16, 2005
    Publication date: June 19, 2008
    Inventors: Hirohito Watanabe, Motofumi Saitou, Hiroshi Sunamura
  • Publication number: 20070284610
    Abstract: Provided is a switching device including ion conducting part 4 having an ion conductor, first electrode 1 formed at a first gap away from ion conducting part 4, second electrode 2 formed to be in contact with ion conducting part 4 and third electrode 3 formed at a second gap away from ion conducting part 4. Second electrode 2 supplies metal ions to the ion conductor, or receives the metal ions from the ion conductor to precipitate metal corresponding to the metal ions.
    Type: Application
    Filed: December 22, 2005
    Publication date: December 13, 2007
    Applicant: NEC CORPORATION
    Inventors: Hisao Kawaura, Hiroshi Sunamura
  • Publication number: 20070285148
    Abstract: The switching element of the present invention is of a configuration that includes: an ion conduction layer (40) that includes an oxide, a first electrode (21) and a second electrode (31) that are provided in contact with the ion conduction layer (40) and that are connected by the precipitate of metal that is supplied from the outside or for which electrical properties change due to the dissolution of precipitated metal, and a third electrode (35) provided in contact with the ion conduction layer (40) and that can supply metal ions. The use of this configuration allows the switching voltage to be set higher than in the related art.
    Type: Application
    Filed: December 27, 2005
    Publication date: December 13, 2007
    Applicant: NEC CORPORATION
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura, Hiroshi Sunamura, Naoki Banno
  • Publication number: 20070132590
    Abstract: When a predetermined voltage is applied between electrodes (302), metal ions deposit in a solid electrolyte (308), and thereby a conduction channel (310) is formed therein. The solid electrolyte switch (300) is thus turned on. Because this deposition mechanism is reversible, application of reverse voltage between the electrodes of the solid electrolyte switch (300) already turned on makes the deposited metal atoms to migrate in the solid electrolyte to thereby thin the conduction channel 300, thereby the channel finally disappears, and the solid electrolyte switch (300) is turned into a non-conductive state. Use of this switch successfully realizes an IC tag which can automatically be nullified without artificial nullification.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 14, 2007
    Inventors: Wataru Hattori, Hiroo Hongo, Fumiyuki Nihei, Hiroshi Sunamura
  • Publication number: 20060273429
    Abstract: A switching element with a switching voltage set higher than conventional, which includes an ion conduction layer including tantalum oxide, a first electrode provided in contact with the ion conduction layer, and a second electrode provided in contact with the ion conduction layer and capable of supplying the ion conduction layer with metal ions.
    Type: Application
    Filed: May 10, 2006
    Publication date: December 7, 2006
    Applicant: NEC CORPORATION
    Inventors: Toshitsugu Sakamoto, Noriyuki Iguchi, Hiroshi Sunamura
  • Patent number: 7116573
    Abstract: A switching element has an ion conductor capable of conducting metal ions for use in an electrochemical reaction therein, a first electrode and a second electrode which are disposed in contact with said ion conductor and spaced a predetermined distance from each other, and a third electrode disposed in contact with the ion conductor. When a voltage for causing the switching element to transit to an on state is applied to the third electrode, metal is precipitated between the first electrode and the second electrode by metal ions, electrically interconnecting the first electrode and the second electrode. When a voltage for causing the switching element to transit to an off state is applied to the third electrode, the precipitated metal is dissolved to electrically disconnect the first electrode and the second electrode from each other.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: October 3, 2006
    Assignee: NEC Corporation
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura, Hiroshi Sunamura
  • Patent number: RE42040
    Abstract: A switching element has an ion conductor capable of conducting metal ions for use in an electrochemical reaction therein, a first electrode and a second electrode which are disposed in contact with said ion conductor and spaced a predetermined distance from each other, and a third electrode disposed in contact with the ion conductor. When a voltage for causing the switching element to transit to an on state is applied to the third electrode, metal is precipitated between the first electrode and the second electrode by metal ions, electrically interconnecting the first electrode and the second electrode. When a voltage for causing the switching element to transit to an off state is applied to the third electrode, the precipitated metal is dissolved to electrically disconnect the first electrode and the second electrode from each other.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: January 18, 2011
    Assignee: NEC Corporation
    Inventors: Toshitsugu Sakamoto, Hisao Kawaura, Hiroshi Sunamura