Patents by Inventor Hiroshi Tsuchi

Hiroshi Tsuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220277704
    Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first voltage follower circuit that supplies a voltage obtained by shifting a voltage of the positive voltage signal supplied to the first node to a negative side by a predetermined voltage difference to a gate of the first switch, and a second voltage follower circuit that supplies a voltage obtained by shifting a voltage of the negative voltage signal supplied to the second node to a positive side by a predetermined voltage difference to a gate of the second switch.
    Type: Application
    Filed: February 15, 2022
    Publication date: September 1, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Publication number: 20220270563
    Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the first node through source follower operation and supplies the gate voltage to a gate of the first switch, and a second follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the second node through source follower operation and supplies the gate voltage to a gate of the second switch.
    Type: Application
    Filed: February 15, 2022
    Publication date: August 25, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventors: Hiroshi TSUCHI, Manabu NISHIMIZU
  • Publication number: 20220246079
    Abstract: The present invention includes first to j-th DA conversion circuits that are fixedly coupled to one of a plurality of gradation reference voltage generating circuits steadily generating respective gradation reference voltage groups according to gamma correction characteristics of color components different from one another, and select a gradation reference voltage corresponding to a pixel data piece among the gradation reference voltage group generated by the one of gradation reference voltage generating circuits to output the gradation reference voltage as a gradation voltage, an output unit that assigns the first to j-th gradation voltages to respective first to j-th driving voltage signals in a mode according to an output switching signal, and outputs the first to j-th driving voltage signals to the display panel, and an output control unit that generates the output switching signal to switch modes of assigning the first to j-th gradation voltages to the first to j-th driving voltage signals at every divis
    Type: Application
    Filed: January 25, 2022
    Publication date: August 4, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventors: Takuro KOTAKI, Atsushi HIRAMA, Hiroshi TSUCHI
  • Patent number: 11398202
    Abstract: Display apparatuses, data drivers and display controller are provided. The data drivers receive video signals, generate positive-polarity and negative-polarity gradation data signals with respect to a predetermined reference voltage based on the video signals, output the positive-polarity gradation data signals to one of a first and a second data line groups, and output the negative-polarity gradation data signals to the other data line group. The data drivers generate, as the positive-polarity gradation data signals, signals in which data pulses each having a positive-polarity analog voltage value corresponding to a luminance level of each pixel based on the video signal appear in predetermined cycles, and generate, as the negative-polarity gradation data signals, signals where data pulses each having a negative-polarity analog voltage value corresponding to a luminance level of each pixel appear in each predetermined cycle with phases different from the positive-polarity gradation data signals.
    Type: Grant
    Filed: July 26, 2020
    Date of Patent: July 26, 2022
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Keigo Otani
  • Publication number: 20220208136
    Abstract: The disclosure includes: first level shift part generating a voltage signal by converting an input voltage signal into amplitude between first negative and positive polarity power supply voltages; second level shift part generating a first polarity voltage signal by converting the voltage signal into amplitude between a reference and the first positive polarity power supply voltage; third level shift part outputting a first-polarity high voltage signal by converting the first polarity voltage signal into amplitude between a higher second positive polarity power supply voltage and the reference; fourth level shift part generating a second polarity voltage signal by converting the voltage signal into amplitude between the reference and the first negative polarity power supply voltage; and fifth level shift part outputting a second-polarity high voltage signal by converting the second polarity voltage signal into amplitude between a lower second negative polarity power supply voltage and the reference.
    Type: Application
    Filed: December 19, 2021
    Publication date: June 30, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventors: Hiroshi TSUCHI, Hayato KOIZUMI
  • Patent number: 11356113
    Abstract: A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: June 7, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20220171227
    Abstract: An output circuit is provided, including: a positive polarity voltage signal supplying circuit to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch of which a source is connected to the first node and a drain is connected to a first output terminal; a second switch of which a source is connected to the second node and a drain is connected to the first output terminal; and third and fourth switches; a first and a second voltage control circuits respectively performing on-off control of the first and second switches.
    Type: Application
    Filed: February 21, 2022
    Publication date: June 2, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Patent number: 11341886
    Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 24, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20220139285
    Abstract: The disclosure provides a display driver and a display device which includes the display driver. A display driver according to the disclosure has a temperature abnormality detection circuit that detects a temperature inside the display driver and generates a temperature abnormality detection signal indicating the presence of a temperature abnormality when the temperature therein is higher than a predetermined temperature threshold, and a temperature abnormality notification processing part that causes a display panel to display an image for informing of occurrence of a temperature abnormality for a predetermined period instead of an image based on a video signal in accordance with the temperature abnormality detection signal.
    Type: Application
    Filed: November 1, 2021
    Publication date: May 5, 2022
    Applicant: LAPIS Technology Co., Ltd.
    Inventors: Hayato KOIZUMI, Hiroshi TSUCHI
  • Publication number: 20220114982
    Abstract: A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.
    Type: Application
    Filed: December 22, 2021
    Publication date: April 14, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi TSUCHI, Koji Higuchi
  • Patent number: 11281034
    Abstract: An output circuit is provided. The disclosure includes: a positive polarity voltage signal supplying circuit configured to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit configured to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch formed from a P channel transistor of which a source and a back gate are connected to the first node and a drain is connected to a first output terminal; a second switch formed from an N channel transistor of which a source and a back gate are connected to the second node and a drain is connected to the first output terminal; and third and fourth switches.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: March 22, 2022
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20220036801
    Abstract: A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to xth input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to xth input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to xth input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.
    Type: Application
    Filed: July 19, 2021
    Publication date: February 3, 2022
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi Tsuchi
  • Patent number: 11232762
    Abstract: In the present invention, a differential amplifier that includes a first output transistor and a second output transistor includes a boost circuit that includes a third output transistor and a fourth output transistor. The first output transistor delivers a current according to a first differential signal generated in a differential stage to an output terminal. The second output transistor extracts a current according to a second differential signal generated as a signal which is the same phase with a different potential of the first differential signal from the output terminal. The third output transistor delivers a current to the output terminal according to a level-shifting signal generated by level-shifting the first differential signal. The fourth output transistor extracts a current from the output terminal according to a level-shifting signal generated by level-shifting the second differential signal.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: January 25, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Tsuchi
  • Patent number: 11217196
    Abstract: A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: January 4, 2022
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Koji Higuchi
  • Patent number: 11200864
    Abstract: A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.
    Type: Grant
    Filed: March 28, 2021
    Date of Patent: December 14, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu
  • Patent number: 11164505
    Abstract: A display apparatus includes: a display panel; a gate driver that provides, to a plurality of scanning lines, scanning pulse signals for controlling pixel switches to be ON in a selection period corresponding to a pulse width thereof; a data driver that provides gradation voltage signals to a plurality of data lines; and a display controller that provides a modulated clock signal having a frequency that changes at a predetermined rate in one frame period. The gate driver sequentially provides the scanning pulse signals each having a pulse width reflecting to a clock cycle of the modulated clock signal in a predetermined order corresponding to distances from the data driver to the plurality of scanning lines. The data driver provides the gradation voltage signals in the order of providing the scanning pulse signals for every data period corresponding to the clock cycle of the modulated clock signal.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 2, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Katsunori Ito
  • Publication number: 20210231992
    Abstract: An output circuit is provided. The disclosure includes: a positive polarity voltage signal supplying circuit configured to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit configured to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch formed from a P channel transistor of which a source and a back gate are connected to the first node and a drain is connected to a first output terminal; a second switch formed from an N channel transistor of which a source and a back gate are connected to the second node and a drain is connected to the first output terminal; and third and fourth switches.
    Type: Application
    Filed: January 13, 2021
    Publication date: July 29, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20210217377
    Abstract: A level voltage generation circuit, a data driver and a display are provided. The level voltage generation circuit generates, based on N different input voltages, M (M>N) level voltages. The level voltage generation circuit comprises N differential amplifiers having output ends, which receive the N input voltages respectively, amplify the N input voltages respectively and output amplified N input voltages, and a resistor ladder having N voltage supply points respectively connected to the output ends of the N differential amplifiers and M voltage output points for outputting the M level voltages. The resistor ladder comprises a first wiring, connected to the output end of one of the N differential amplifiers through one of the N voltage supply points; and a second wiring, connected between one of the M voltage output points and one of an input pair of one of the N differential amplifiers.
    Type: Application
    Filed: March 28, 2021
    Publication date: July 15, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu
  • Publication number: 20210183328
    Abstract: A source driver includes a data latch unit that outputs acquired pixel data, a gradation voltage conversion unit that acquires the pixel data outputted from the data latch unit and converts the pixel data to gradation voltages, an output unit that amplifies and outputs the gradation voltages to source lines, and a timing control unit that controls the timing of the output of the pixel data from the data latch unit. The timing control unit performs control such that the longer a source line is from a source driver to a pixel column, the smaller the timing difference is between acquisition of the pixel data by the data latch unit and the output of the pixel data.
    Type: Application
    Filed: December 8, 2020
    Publication date: June 17, 2021
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Naoki TANIGUCHI, Hiroshi TSUCHI, Takashi OHNO
  • Patent number: 10964287
    Abstract: The display apparatus includes: N differential amplifiers having output ends, amplifying N input voltages and outputting amplified voltages, and a resistor ladder having N voltage supply points connected to the output ends of the N differential amplifiers and M voltage output points outputting M level voltages. The M voltage output points are connected to capacitive loads on input sides of the amplifiers, and at least one N differential amplifier has an input pair and an output end connected to one of the N voltage supply point. One of the N input voltages is received by one of the input pair, the other one of the input pair is connected to one of the M voltage output points outputting a level voltage closest to a voltage at the one voltage supply point. The one voltage supply point and the one voltage output point are at different positions on the resistor ladder.
    Type: Grant
    Filed: September 17, 2020
    Date of Patent: March 30, 2021
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu