Abstract: The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

Abstract: The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

Abstract: An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.

Abstract: A digital-to-analog conversion circuit includes a differential amplifier outputting 2N voltage levels dividing first and second voltages and a decoder distributing and supplying one of first and second voltages to a plurality of input terminals of the differential amplifier on the basis of digital data of N bits, and the differential amplifier includes 2K differential pairs including an inverting input terminal to which an output voltage is commonly input and a non-inverting input terminal to which one of voltages received by the plurality of input terminals is input and having output pairs commonly connected with each other and a tail current control circuit individually controlling current ratios of tail currents supplied to the differential pairs on the basis of a predetermined bit of digital data, in which N is equal to or greater than 3, and K is a positive number less than N.

Abstract: Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current>the first current, the second current>the fourth current.

Abstract: Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current >the first current, the second current >the fourth current.

Abstract: The disclosure includes multiple data drivers provided for each predetermined number of data lines. Each data driver receives an image signal; generates, based on the image signal, a positive gradation data signal and a negative gradation data signal; outputs one of the positive and negative gradation data signals to one of a first and second data line groups of a display panel; and outputs the other of the positive and negative gradation data signals to the other of the first and second data line groups. The data driver shifts a phase of the negative gradation data signal in a direction delayed with respect to the positive gradation data signal, and controls a slew rate of an output amplifier for outputting the positive gradation data signal to be lower than that of an output amplifier for outputting the negative gradation data signal.

Abstract: The present invention includes first to j-th DA conversion circuits that are fixedly coupled to one of a plurality of gradation reference voltage generating circuits steadily generating respective gradation reference voltage groups according to gamma correction characteristics of color components different from one another, and select a gradation reference voltage corresponding to a pixel data piece among the gradation reference voltage group generated by the one of gradation reference voltage generating circuits to output the gradation reference voltage as a gradation voltage, an output unit that assigns the first to j-th gradation voltages to respective first to j-th driving voltage signals in a mode according to an output switching signal, and outputs the first to j-th driving voltage signals to the display panel, and an output control unit that generates the output switching signal to switch modes of assigning the first to j-th gradation voltages to the first to j-th driving voltage signals at every divis

Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first voltage follower circuit that supplies a voltage obtained by shifting a voltage of the positive voltage signal supplied to the first node to a negative side by a predetermined voltage difference to a gate of the first switch, and a second voltage follower circuit that supplies a voltage obtained by shifting a voltage of the negative voltage signal supplied to the second node to a positive side by a predetermined voltage difference to a gate of the second switch.

Abstract: An output circuit is provided, including: a positive polarity voltage signal supplying circuit to supply or block the supply of a positive polarity voltage signal having a voltage higher than a reference power source voltage to a first node; a negative polarity voltage signal supplying circuit to supply or block the supply of a negative polarity voltage signal having a voltage lower than the reference power source voltage to a second node; a first switch of which a source is connected to the first node and a drain is connected to a first output terminal; a second switch of which a source is connected to the second node and a drain is connected to the first output terminal; and third and fourth switches; a first and a second voltage control circuits respectively performing on-off control of the first and second switches.

Abstract: In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

Abstract: A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to xth input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to xth input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to xth input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

Abstract: Provided is an output amplifier having: a push-pull output-stage formed by first and second output-stage transistors; and a detection circuit detecting an abnormal output current output by the output amplifier and including: a coupling circuit, generating first and second currents mirroring current flowing in the first output-stage transistor and third and fourth currents mirroring current flowing in the second output-stage transistor, coupling the first and third currents at a first output node, outputting a first voltage at the first output node, coupling the second and fourth currents at a second output node, and outputting a second voltage at the second output node; and a determination circuit, outputting a determination signal indicating normality of an output current based on the first and second voltages. The coupling circuit generates the first to fourth currents. In the reference state, the third current > the first current, the second current > the fourth current.

Abstract: Provided is a display device including: a display panel including data lines extending in a vertical direction of a two-dimensional screen and each connected to a pixel for displaying one of multiple primary colors; and a data driver that supplies gradation data signals having voltage values corresponding to a brightness level of each pixel based on an image signal to the display panel via output terminals, and performs a time division drive on the data lines in a first to M-th division periods of each horizontal scanning period in the image signal. The display panel includes a time division switch for every M data lines to which the pixels for displaying a same primary color are connected, and the time division switch sequentially selects the M data lines one by one in each of the first to M-th division periods and connects the selected data line to one output terminal.

Abstract: A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.

Abstract: An output circuit includes a first switch that outputs a positive voltage signal received via a first node when in an ON state, a second switch that outputs a negative voltage signal received via a second node when in an ON state, third and fourth switches that set the first and second nodes to a reference power supply voltage when in an ON state, a first follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the first node through source follower operation and supplies the gate voltage to a gate of the first switch, and a second follower circuit that generates, as a gate voltage, a voltage signal following and being in phase with a voltage signal of the second node through source follower operation and supplies the gate voltage to a gate of the second switch.

Abstract: The disclosure includes multiple data drivers provided for each predetermined number of data lines. Each data driver receives an image signal; generates, based on the image signal, a positive gradation data signal and a negative gradation data signal; outputs one of the positive and negative gradation data signals to one of a first and second data line groups of a display panel; and outputs the other of the positive and negative gradation data signals to the other of the first and second data line groups. The data driver shifts a phase of the negative gradation data signal in a direction delayed with respect to the positive gradation data signal, and controls a slew rate of an output amplifier for outputting the positive gradation data signal to be lower than that of an output amplifier for outputting the negative gradation data signal.

Abstract: The disclosure provides a display driver and a display device which includes the display driver. A display driver according to the disclosure has a temperature abnormality detection circuit that detects a temperature inside the display driver and generates a temperature abnormality detection signal indicating the presence of a temperature abnormality when the temperature therein is higher than a predetermined temperature threshold, and a temperature abnormality notification processing part that causes a display panel to display an image for informing of occurrence of a temperature abnormality for a predetermined period instead of an image based on a video signal in accordance with the temperature abnormality detection signal.

Abstract: A source driver includes a data latch unit that outputs acquired pixel data, a gradation voltage conversion unit that acquires the pixel data outputted from the data latch unit and converts the pixel data to gradation voltages, an output unit that amplifies and outputs the gradation voltages to source lines, and a timing control unit that controls the timing of the output of the pixel data from the data latch unit. The timing control unit performs control such that the longer a source line is from a source driver to a pixel column, the smaller the timing difference is between acquisition of the pixel data by the data latch unit and the output of the pixel data.

Abstract: The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.