Abstract: An output amplifier circuit, and a display driver and a display device including the output amplifier circuit. The output amplifier circuit includes: first to nth amplifiers which receive first to nth input voltages and generate first to nth output voltages by amplifying the respective first to nth input voltages; first to Kth bias circuits which are provided corresponding to each of first to Kth amplifier groups formed by grouping the first to nth amplifiers into K groups, and each generates a bias voltage for setting a current value of an operating current of the amplifiers; first to Kth wirings which supply the bias voltage generated by each of the first to Kth bias circuits to the first to Kth amplifier groups respectively; and a switch circuit which, when in an ON state, connects one wiring among the first to Kth wirings with another wiring different from the one wiring.

Abstract: The disclosure includes: a first transistor, supplying a first power voltage to the output terminal when becoming ON according to a voltage of the input signal received by a gate; a second transistor, supplying a second power voltage to the output terminal in a case of becoming ON in accordance with the voltage of the input signal received by a gate; and an output control part, transitioning to ON by changing a voltage of the gate of the transistor in OFF between the first and second transistors at a change speed based on a current value of a bias current generated by a bias part when the voltage of the input signal changes. According to a voltage change of the input signal, the bias part sets a bias current value to a first value throughout a predetermined period, and switches to a second, lower value in other periods.

Abstract: A digital-to-analog converter for effectively performing offset cancellation driving to reduce output variations includes: a decoder receiving a K-bit digital data signal and first and second voltages and generating 2K voltages each indicating the first or second voltage according to the digital data signal; and a differential amplifier outputting an output voltage having one of 2K voltage levels obtained by dividing the voltage between the first and second voltages into 2K voltage levels. The differential amplifier includes a MUX receiving 2K voltages, 2K differential pairs, and an amplification stage to which outputs of the 2K differential pairs are supplied. The MUX performs voltage supply to input terminals of each differential pair to actively cause that, in each differential pair, the input voltage to one input terminal in a first state differs from the input voltage to the other input terminal in a subsequent second state.

Abstract: An output buffer circuit includes a first transistor supplying a first high-voltage power supply voltage in a case of being ON in response to a voltage of an input signal received through a gate; a second transistor supplying a second high-voltage power supply voltage in the case of being ON in response to a voltage of the input signal received through a gate; an output control part that shifts a transistor, of the first and second transistors, being ON to OFF at a time of voltage change of the input signal by changing the voltage in the gate thereof, and turns a transistor being OFF to ON by changing the voltage in the gate thereof at a rate of change based on a current value controlled by a bias voltage, and a bias modulation part that sets a voltage value of the bias voltage to a designated voltage value.

Abstract: The disclosure includes: a decoder generating multiple input voltages each having one or the other of two reference voltages selected from multiple reference voltages, using a high voltage digital data signal obtained by increasing the amplitude of a low voltage digital data signal; and a differential amplifier including multiple differential pairs and receiving the input voltages at the non-inverting input terminals of the differential pairs and receiving an output voltage signal at the inverting input terminals to generate an output voltage signal having one of the voltage levels obtained by dividing the two reference voltages into a power of 2. The differential amplifier includes: multiple current sources generating tail currents flowing through the tails of the differential pairs; and multiple clamp transistors provided respectively between the tails of the differential pairs and the current sources and holding a voltage applied to each current source at or below a low voltage.

Abstract: The differential amplifier circuit includes: first conductivity type first to Nth differential stages each causing a current corresponding to the first or second voltage received at the non-inverting input terminal to flow to a first node and a current corresponding to the output voltage signal received at the inverting input terminal to a second node; a second conductivity type differential stage receiving one of the first and second voltages at the non-inverting input terminal and receiving the output voltage signal at the inverting input terminal, and being activated when the digital data value is within a predetermined range to cause a current corresponding to the one voltage to flow to a third node and a current corresponding to the output voltage signal to a fourth node; and an output amplification stage generating the output voltage signal based on the currents respectively flowing to the first to fourth nodes.

Abstract: A digital-to-analog converter for effectively performing offset cancellation driving to reduce output variations includes: a decoder receiving a K-bit digital data signal and first and second voltages and generating 2K voltages each indicating the first or second voltage according to the digital data signal; and a differential amplifier outputting an output voltage having one of 2K voltage levels obtained by dividing the voltage between the first and second voltages into 2K voltage levels. The differential amplifier includes a MUX receiving 2K voltages, 2K differential pairs, and an amplification stage to which outputs of the 2K differential pairs are supplied. The MUX performs voltage supply to input terminals of each differential pair to actively cause that, in each differential pair, the input voltage to one input terminal in a first state differs from the input voltage to the other input terminal in a subsequent second state.

Abstract: An output amplifier circuit includes: 1st to K-th sub-bias circuits configured to be disposed in correspondence with 1st to K-th amplifier groups acquired by dividing 1st to n-th amplifiers for every predetermined number of amplifiers, generate a plurality of bias voltages for setting current values of operation currents of the amplifiers, and supply the bias voltages to amplifiers belonging to corresponding amplifier groups; and a main bias circuit configured to supply K currents having current values corresponding to voltage values designated by a control signal designating the voltage values of bias voltages to the 1st to K-th sub-bias circuits as 1st to K-th bias control currents, in which the 1st to K-th sub-bias circuits generate the plurality of bias voltages based on voltages acquired by performing current-to-voltage conversion on the bias control currents received by the sub-bias circuits among the 1st to K-th bias control currents.

Abstract: In the disclosure, in generating an output voltage that is stepped up or down to a target voltage value by repeatedly charging/discharging a capacitor according to a charge pump driving signal, before a voltage value of the output voltage reaches a target voltage value, driving capability of an output buffer that generates the charge pump driving signal is decreased.

Abstract: The disclosure includes: a first transistor, supplying a first power voltage to the output terminal when becoming ON according to a voltage of the input signal received by a gate; a second transistor, supplying a second power voltage to the output terminal in a case of becoming ON in accordance with the voltage of the input signal received by a gate; and an output control part, transitioning to ON by changing a voltage of the gate of the transistor in OFF between the first and second transistors at a change speed based on a current value of a bias current generated by a bias part when the voltage of the input signal changes. According to a voltage change of the input signal, the bias part sets a bias current value to a first value throughout a predetermined period, and switches to a second, lower value in other periods.

Abstract: The disclosure includes a differential amplifier and a first decoder that distributes and supplies a first or a second voltage to each of a plurality of input terminals based on digital data. The differential amplifier includes a Kth-power of 2 pieces of differential pairs each driven by an individually received tail current, and a tail current control circuit that individually supplies the tail current to the Kth-power of 2 pieces of the differential pairs. The tail current control circuit sets a current ratio of the tail current flowing through of two respective differential pairs among the Kth-power of 2 pieces of the differential pairs to be larger than a current ratio of the tail current flowing through other respective differential pairs excluding the two differential pairs.

Abstract: The disclosure includes: first level shift part generating a voltage signal by converting an input voltage signal into amplitude between first negative and positive polarity power supply voltages; second level shift part generating a first polarity voltage signal by converting the voltage signal into amplitude between a reference and the first positive polarity power supply voltage; third level shift part outputting a first-polarity high voltage signal by converting the first polarity voltage signal into amplitude between a higher second positive polarity power supply voltage and the reference; fourth level shift part generating a second polarity voltage signal by converting the voltage signal into amplitude between the reference and the first negative polarity power supply voltage; and fifth level shift part outputting a second-polarity high voltage signal by converting the second polarity voltage signal into amplitude between a lower second negative polarity power supply voltage and the reference.

Abstract: The disclosure includes: a differential amplifier, and a first decoder assigning and supplying a first or second voltage to each of a plurality of input terminals based on (K+1) bits of digital data. The differential amplifier includes 2K differential pairs each driven by a tail current received individually, and a tail current control circuit supplying first to 2Kth tail currents to the 2K differential pairs and controlling first to 2Kth current ratios for the first to 2Kth tail currents based on the digital data. The tail current control circuit has a basic configuration that sets each of the first to 2Kth current ratios to a maximum value, a minimum value, or an intermediate value among three predetermined values, and increases one of the maximum and minimum values and decreases the other for the current ratio of the tail currents supplied to two predetermined differential pairs.

Abstract: The disclosure includes: a decoder generating multiple input voltages each having one or the other of two reference voltages selected from multiple reference voltages, using a high voltage digital data signal obtained by increasing the amplitude of a low voltage digital data signal; and a differential amplifier including multiple differential pairs and receiving the input voltages at the non-inverting input terminals of the differential pairs and receiving an output voltage signal at the inverting input terminals to generate an output voltage signal having one of the voltage levels obtained by dividing the two reference voltages into a power of 2. The differential amplifier includes: multiple current sources generating tail currents flowing through the tails of the differential pairs; and multiple clamp transistors provided respectively between the tails of the differential pairs and the current sources and holding a voltage applied to each current source at or below a low voltage.

Abstract: In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

Abstract: An output buffer circuit includes a first transistor supplying a first high-voltage power supply voltage in a case of being ON in response to a voltage of an input signal received through a gate; a second transistor supplying a second high-voltage power supply voltage in the case of being ON in response to a voltage of the input signal received through a gate; an output control part that shifts a transistor, of the first and second transistors, being ON to OFF at a time of voltage change of the input signal by changing the voltage in the gate thereof, and turns a transistor being OFF to ON by changing the voltage in the gate thereof at a rate of change based on a current value controlled by a bias voltage, and a bias modulation part that sets a voltage value of the bias voltage to a designated voltage value.

Abstract: The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

Abstract: The disclosure includes: a bias circuit generating first and second bias voltages; a first conductivity type first transistor supplying a first power source voltage to a first node according to the input signal; a second conductivity type second transistor supplying a second power source voltage to a second node according to the input signal; a second conductivity type third transistor receiving the first bias voltage by gate, with source and drain connected to the second and first nodes; a first conductivity type fourth transistor receiving the second bias voltage by gate, with source and drain connected to the first and second nodes; a first conductivity type fifth transistor supplying the first power source voltage to an output terminal according to voltage at the first node; and a second conductivity type sixth transistor supplying the second power source voltage to the output terminal according to voltage at the second node.

Abstract: A digital-to-analog conversion circuit includes a differential amplifier outputting 2N voltage levels dividing first and second voltages and a decoder distributing and supplying one of first and second voltages to a plurality of input terminals of the differential amplifier on the basis of digital data of N bits, and the differential amplifier includes 2K differential pairs including an inverting input terminal to which an output voltage is commonly input and a non-inverting input terminal to which one of voltages received by the plurality of input terminals is input and having output pairs commonly connected with each other and a tail current control circuit individually controlling current ratios of tail currents supplied to the differential pairs on the basis of a predetermined bit of digital data, in which N is equal to or greater than 3, and K is a positive number less than N.

Abstract: An output buffer circuit includes: a first transistor supplying a first power supply voltage to a first node upon turning on in response to an input signal; a second transistor supplying a second power supply voltage to a second node upon turning on in response to the input signal; a third transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the first node; a fourth transistor connecting between the first and second nodes upon turning on in response to a reverse phase signal of a signal on the second node; a fifth transistor supplying the first power supply voltage upon turning on in response to the signal on the first node; and a sixth transistor supplying the second power supply voltage upon turning on in response to the signal on the second node.