Abstract: A level shift circuit is configured to receive reference voltage and first to third voltages, and to generate an output signal. The voltages satisfy a condition in which the reference voltage<the first voltage<the second voltage<the third voltage or the reference voltage>the first voltage>the second voltage>the third voltage. The level shift circuit includes a first level shift circuit configured to receive a first signal having a first amplitude within a difference between the reference and first voltages, and level shift the first signal to a second signal having a second amplitude within a difference between the reference and second voltages, and a second level shift circuit configured to level shift the second signal to a third signal having a third amplitude within a difference between the reference and third voltages, and output the third signal as the output signal.

Abstract: A differential amplifier circuit includes a differential input stage, a first current mirror, a second current mirror, a first current source circuit, and a second current source circuit. The first current source circuit has a first transistor of a first conductivity type with a control terminal supplied with a first bias voltage, and a second transistor of a second conductivity type with a control terminal supplied with a second bias voltage. An output amplifier circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. A control circuit has a fifth transistor of the first conductivity type with a first terminal connected to a connection point between the other end of the second current source circuit and the control terminal of the fourth transistor in the output amplifier circuit, with a second terminal connected to an output node of the second current mirror, and with a control terminal receiving the first bias voltage.

Abstract: A level shift circuit configured to generate an output signal having higher amplitude than that of an input signal. The level shift circuit includes serially-connected first and second level shift circuit for two-step amplitude increase of the input signal. The first level shift circuit includes first to fourth transistors, each of which has a control terminal and first and second current terminals, and first and second resistance elements respectively connected between the first and third transistors, and between the second and fourth transistors. A potential difference between two ends of each resistance element is respectively smaller than, or no smaller than, a respective predetermined potential difference when a current does not flow, or flows, therethrough. The second level shift circuit has fifth to tenth transistors, each of which has a control terminal and first and second current terminals.

Abstract: A display device includes an output circuit including a differential amplifier circuit, an output amplifier circuit that includes a first transistor of the first conduction type coupled between the first supply terminal and the output terminal, and including a control terminal coupled to the differential amplifier circuit, a first control circuit, an input terminal, an output terminal, and first to third supply terminals to which first to third supply voltages are applied, wherein the third supply voltage is set to a voltage between the first supply voltage and the second supply voltage, or the second supply voltage, and wherein the first control circuit includes a third transistor and a first switch which are coupled in series between the first supply terminal and the control terminal of the first transistor.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A level shift circuit configured to generate an output signal having higher amplitude than that of an input signal. The level shift circuit includes serially-connected first and second level shift circuit for two-step amplitude increase of the input signal. The first level shift circuit includes first to fourth transistors, each of which has a control terminal and first and second current terminals, and first and second resistance elements respectively connected between the first and third transistors, and between the second and fourth transistors. A potential difference between two ends of each resistance element is respectively smaller than, or no smaller than, a respective predetermined potential difference when a current does not flow, or flows, therethrough. The second level shift circuit has fifth to tenth transistors, each of which has a control terminal and first and second current terminals.

Abstract: DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2?n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A?1+2?n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A?4+2?n) and (A+2?n), and an at most {?4+2?(n?2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {?3+2?(n?2)} reference voltages that are other than the four number of reference voltages from the {1+2?(n?2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2?(n?2).

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A data driver including an output circuit configured to output an output signal, and a driver output terminal configured to be connected with a display panel and provide the output signal to the display panel. The output circuit includes a buffer having an output coupled with an input of a first switch and an input of a second switch, an output protective resistor coupled between the driver output terminal and an output of the second switch, and a compensation resistor coupled in series with the first switch and between the output of the buffer and the output protective resistor.

Abstract: DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2^n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A?1+2^n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A?4+2^n) and (A+2^n), and an at most {?4+2^(n?2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {?3+2^(n?2)} reference voltages that are other than the four number of reference voltages from the {1+2^(n?2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2^(n?2).

Abstract: Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, while the second and fourth sub-decoder sections are made up of second conductivity type transistors.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: A data driver for display panels includes: multiple driver output terminals coupled to multiple data lines of a display panel; and multiple output circuits that output output signals from the driver output terminals. Each output circuit includes: an output buffer that outputs an output signal; a first resistor having one end coupled to one of the driver output terminals; a first switch and a second resistor coupled in series between an output node of the output buffer and the other end of the first resistor; and a second switch coupled in parallel to the first switch and the second resistor between the output node of the output buffer and the other end of the first resistor.

Abstract: A display driver circuit includes an input terminal configured to receive an input signal, an output terminal configured to output an output signal, a slew rate control circuit configured to input the input signal and the output signal, and output a pair of differential input signals based on a voltage difference between the input signal and the output signal; a differential input circuit configured to input the pair of the differential input signals and output a pair of differential output signals, wherein the differential input circuit includes a first current mirror circuit and a second current mirror circuit, and an output circuit configured to input the pair of the differential output signals and output the output signal to the output terminal.

Abstract: A display device includes an output circuit including a differential amplifier circuit, an output amplifier circuit that includes a first transistor of the first conduction type coupled between the first supply terminal and the output terminal, and including a control terminal coupled to the differential amplifier circuit, a first control circuit, an input terminal, an output terminal, and first to third supply terminals to which first to third supply voltages are applied, wherein the third supply voltage is set to a voltage between the first supply voltage and the second supply voltage, or the second supply voltage, and wherein the first control circuit includes a third transistor and a first switch which are coupled in series between the first supply terminal and the control terminal of the first transistor.

Abstract: A display driver circuit includes an input terminal configured to receive an input signal, an output terminal configured to output an output signal, a slew rate control circuit configured to input the input signal and the output signal, and output a pair of differential input signals based on a voltage difference between the input signal and the output signal; a differential input circuit configured to input the pair of the differential input signals and output a pair of differential output signals, wherein the differential input circuit includes a first current mirror circuit and a second current mirror circuit, and an output circuit configured to input the pair of the differential output signals and output the output signal to the output terminal.

Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.