Abstract: A display device includes an output circuit including a differential amplifier circuit, an output amplifier circuit that includes a first transistor of the first conduction type coupled between the first supply terminal and the output terminal, and including a control terminal coupled to the differential amplifier circuit, a first control circuit, an input terminal, an output terminal, and first to third supply terminals to which first to third supply voltages are applied, wherein the third supply voltage is set to a voltage between the first supply voltage and the second supply voltage, or the second supply voltage, and wherein the first control circuit includes a third transistor and a first switch which are coupled in series between the first supply terminal and the control terminal of the first transistor.

Abstract: A display driver circuit includes an input terminal configured to receive an input signal, an output terminal configured to output an output signal, a slew rate control circuit configured to input the input signal and the output signal, and output a pair of differential input signals based on a voltage difference between the input signal and the output signal; a differential input circuit configured to input the pair of the differential input signals and output a pair of differential output signals, wherein the differential input circuit includes a first current mirror circuit and a second current mirror circuit, and an output circuit configured to input the pair of the differential output signals and output the output signal to the output terminal.

Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit, input and output terminals, and first to third supply terminals applied with first to third supply voltages, respectively. The third supply voltage is set a voltage between the first and second supply voltages. The differential amplifier circuit differentially receives signals of the input and output terminals. The output amplifier circuit includes first and second transistors of different conduction type each other coupled in series between the first and third supply terminals via the output terminal, and having control terminals coupled to first and second output nodes of the differential amplifier circuit, respectively. The control circuit includes a third transistor and a switch, and controls the third transistor being in a diode coupling mode between the first supply terminal and the control terminal of the first transistor for a given period of the output period.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: Disclosed is a level shift circuit that includes a first transistor of a first conductivity type connected between a first power supply line and a first node, and second and third transistors of a second conductivity type connected in series between a second power supply line and the first node. A first control signal is supplied in common to a gate of the first transistor and a gate of one of the second and third transistors. A gate of the other of the second and third transistors is connected to an input terminal to which an input signal with an amplitude lower than a power supply amplitude of the first and second power supplies is supplied.

Abstract: An output circuit is capable of supporting a high-speed operation, suppressing power consumption, and controlling its area. The output circuit has a differential input stage, an output amplification stage, and an amplification boost circuit, in which the amplification boost circuit has a differential pair of a second conductivity type and load element pair, and includes a first current source circuit for controlling current supply to an input node of a second current mirror circuit of the differential input stage and boost the charging operation of the output amplification stage according to a voltage difference between input and output voltages, and a second current source circuit for controlling current supply to an output node of a first current mirror circuit of the differential input stage and boost the discharging operation of the output amplification stage.

Abstract: Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, whilst the second and fourth sub-decoder sections are made up of second conductivity type transistors.

Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.

Abstract: Provided first and second reference voltage set wherein the first reference voltage set includes a part or all of reference voltages of the second reference voltage set, and a decoder including first and second sub-decoder sections that select Q reference voltages from first and second reference voltage sets according to upper bits of the input digital signal and transfer the so selected reference voltages to the first to Qth nodes, and third and fourth sub-decoder sections that select first and second voltages from the Q reference voltages transferred to the first to Qth nodes according to lower bits of the input digital signal and transfer the so selected voltages to the first to Pth nodes. The first and third sub-decoder sections are made up of first conductivity type transistors, while the second and fourth sub-decoder sections are made up of second conductivity type transistors.

Abstract: Reference voltages of a reference voltage ensemble are classed into first to (z×S+1)th reference voltage groups, where S is a power of 2 inclusive of 1 and z is a power of 2 plus 1. A decoder includes first to (z×S+1)th sub-decoders provided in association with the first to (z×S+1)th reference voltage groups, and a (z×S+1) input and 2 output type sub-decoder. The first to (z×S+1)th sub-decoders select, from the reference voltage of the first to the (z×S+1)th reference voltage groups, those reference voltages allocated to columns in a two-dimensional array of the reference voltages associated with the values of a first bit group of an input digital signal. The (z×S+1) input and 2 output sub-decoder receives outputs of the first to (z×S+1)th sub-decoders to select the first and second voltages from the reference voltages selected by the first to (z×S+1)th sub-decoders in response to the value of a second bit group of the input digital signal.

Abstract: There is provided a decoder in which a matrix of transistors, a plurality of reference voltage signal lines arranged on a first interconnect layer and extended in a row direction, being separated to one another over the matrix, and a plurality of reference voltage signal lines arranged on a second interconnect layer and extended in the row direction, being separated to one another over the matrix. The reference voltage signal lines on the mutually different layers are respectively connected to impurity diffusion layers of the transistors that are adjacent in the row direction. The reference voltage signal lines on the mutually different layers are respectively connected to the impurity diffusion layers of the transistors that are adjacent in a column direction.

Abstract: Disclosed is an output circuit including a differential amplifier stage, an output amplifier stage, an amplification acceleration circuit and a capacitance connection control circuit. The output amplifier stage includes push/pull type transistors connected an output terminal. The amplification acceleration circuit includes a first switch and a first transistor, connected between a first output of the differential amplifier stage and the output terminal, and a second transistor and a second switch connected between the output terminal and a second output of the differential amplifier stage. The capacitance connection control circuit includes first capacitive element having first end connected to the output terminal, a first switch connected between a second end of the first capacitive element and a first voltage supply terminal, and a second switch connected between the second end of the first capacitive element and one output of a first differential pair of the differential amplifier stage.

Abstract: A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

Abstract: An output circuit includes a differential input stage, an output amplifier stage, a current control circuit; an input terminal, an output terminal.

Abstract: DAC includes a decoder that receives N number of reference voltages and an n-bit digital signal (n 4) to select first to third voltages, and an operational amplifier to output (first voltage+second voltage+2 third voltage)/4 voltage. The operational amplifier is able to output, for respective 2?n combinations of the n-bit digital signal, voltage levels from an Ath level, as a base level, to an (A?1+2?n)th level. The N number of reference voltages include Ath level, (A+4)th level, (A?4+2?n) and (A+2?n), and an at most {?4+2?(n?2)} reference voltages obtained by decimating a pre-set at least one reference voltage from {?3+2?(n?2)} reference voltages that are other than the four number of reference voltages from the {1+2?(n?2)} reference voltages corresponding to the voltage levels spaced each other at an interval of 4 levels from the Ath level. N is not less than 4 and not more than 2?(n?2).

Abstract: A decoder includes a first sub-decoder that receives a first level voltage set and outputs voltages selected according to lower L-bits of N-bit data, a second sub-decoder that receives a second level voltage set and outputs voltages selected according to the lower L-bits, a third sub-decoder that selects, according to higher M-bits, one voltage from the voltages selected by the first and second sub-decoders, a fourth sub-decoder that outputs voltages selected according to lower P-bits from among a third level voltage set, a fifth sub-decoder that selects one voltage selected according to higher Q-bits from the voltages output from the fourth sub-decoder, and a sixth sub-decoder that controls conduction and non-conduction based on K-bits, between one output among outputs of the first sub-decoder, and one output among outputs of the fourth sub-decoder; output of the third sub-decoder and output of the fifth sub-decoder are connected to an output terminal; the first, second, and third sub-decoders are configured

Abstract: An output circuit includes a differential amplifier circuit, an output amplifier circuit, a control circuit. The third power supply voltage is intermediate between the first and second power supply voltages. The differential amplifier circuit includes, between the first and second power supplies, a differential input stage, first and second current mirror and first and second junction circuits. The output amplifier circuit includes first and second transistors connected between the first and third power supplies. The control circuit includes a third transistor connected between the output of the second current mirror and an end of the second junction circuit and supplied with a bias signal having a voltage in accordance with the third power supply voltage.

Abstract: An output amplifier includes a differential stage having a reference voltage supplied to a first input, a first output stage that receives an output of the differential stage, a second output stage whose output is connected to a load, a capacitor element having a first end connected to a second input of the differential stage, and connection control circuits that control switching of first and second connection modes. In the first connection mode, there are provided a non-conductive state between output of the differential stage and input of the second output stage, a non-conductive state between output of the first output stage and output of the second output stage, a conductive state between output of the first output stage and the second input of the differential stage, and voltage of a second end of the capacitor element is an input voltage from the input terminal.

Abstract: A display panel driver includes a color reducing circuit and a driving section. The driving section is configured to drive a first pixel and a second pixel. If a second input image data and a third input image data corresponding to the second pixel are supplied as an image data of a second image display format, then the color reducing circuit generates a third color reduction image data and a fourth color reduction image data. If the first input image data is supplied as the image data of the first image display format, then the first selector selects the third error value, and if the second input image data and the third input image data are supplied as the image data of the second image display format, then the first selector selects the second error value.

Abstract: A differential amplifier has first and second input terminals (T1, T2), an output terminal, a differential stage connected to the first and second input terminals, and an amplification stage having an input terminal thereof connected to an output terminal of the differential stage and an output terminal thereof connected to the output terminal. The differential stage includes a first differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the output terminal, a second differential pair with one of an input pair thereof connected to the first input terminal (T1) and the other connected to the second input terminal (T2), a first current source for supplying current to the first differential pair, a second current source for supplying current to the second differential pair, and a load circuit connected to the output pairs of the first and second differential pairs.