Patents by Inventor Hiroshi Tsuchi

Hiroshi Tsuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10867541
    Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: December 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20200312264
    Abstract: In the present invention, a differential amplifier that includes a first output transistor and a second output transistor includes a boost circuit that includes a third output transistor and a fourth output transistor. The first output transistor delivers a current according to a first differential signal generated in a differential stage to an output terminal. The second output transistor extracts a current according to a second differential signal generated as a signal which is the same phase with a different potential of the first differential signal from the output terminal. The third output transistor delivers a current to the output terminal according to a level-shifting signal generated by level-shifting the first differential signal. The fourth output transistor extracts a current from the output terminal according to a level-shifting signal generated by level-shifting the second differential signal.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 1, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Publication number: 20200295775
    Abstract: A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance.
    Type: Application
    Filed: February 25, 2020
    Publication date: September 17, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Publication number: 20200294437
    Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.
    Type: Application
    Filed: February 25, 2020
    Publication date: September 17, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Patent number: 10777119
    Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 15, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu, Yuushi Syutou
  • Patent number: 10713995
    Abstract: An output circuit includes a differential amplifier including an inverting input terminal, non-inverting input terminals and an output terminal, and outputs, from the output terminal, a voltage having a level corresponding to a weighted average of respective input voltage levels of the non-inverting input terminals, when the output voltage level is equal to a input voltage level of the inverting input terminal, and outputs a voltage having a level corresponding to a difference between a level corresponding to a weighted average of the respective input voltage levels of the non-inverting input terminals and the input voltage level, when which the output voltage level is different from the input voltage level; and a delay circuit that generates a delay voltage responding with a predetermined time constant with respect to a change in the output voltage level and supplies the delay voltage to the inverting input terminal.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 14, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Takeshi Nosaka, Koji Higuchi
  • Publication number: 20200168175
    Abstract: A display device and data driver are provided. The display device includes a plurality of data drivers provided for a predetermined number of data lines in a plurality of data lines. The plurality of data drivers receive the serialized video data signal from the display controller, generate a modulated data timing signal whose period changes within the one frame period, and supply a gradation voltage signal to each of the predetermined number of data lines for each of data periods based on a data timing of the modulated data timing signal, each of data periods corresponding to the data timing of the modulated data timing signal.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 28, 2020
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Koji Higuchi
  • Publication number: 20200152112
    Abstract: A display apparatus includes: a display panel; a gate driver that provides, to a plurality of scanning lines, scanning pulse signals for controlling pixel switches to be ON in a selection period corresponding to a pulse width thereof; a data driver that provides gradation voltage signals to a plurality of data lines; and a display controller that provides a modulated clock signal having a frequency that changes at a predetermined rate in one frame period. The gate driver sequentially provides the scanning pulse signals each having a pulse width reflecting to a clock cycle of the modulated clock signal in a predetermined order corresponding to distances from the data driver to the plurality of scanning lines. The data driver provides the gradation voltage signals in the order of providing the scanning pulse signals for every data period corresponding to the clock cycle of the modulated clock signal.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 14, 2020
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi TSUCHI, Katsunori ITO
  • Patent number: 10650770
    Abstract: A differential amplifier circuit includes a differential input stage, a first current mirror, a second current mirror, a first current source circuit, and a second current source circuit. The first current source circuit has a first transistor of a first conductivity type with a control terminal supplied with a first bias voltage, and a second transistor of a second conductivity type with a control terminal supplied with a second bias voltage. An output amplifier circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. A control circuit has a fifth transistor of the first conductivity type with a first terminal connected to a connection point between the other end of the second current source circuit and the control terminal of the fourth transistor in the output amplifier circuit, with a second terminal connected to an output node of the second current mirror, and with a control terminal receiving the first bias voltage.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 12, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroshi Tsuchi
  • Patent number: 10607560
    Abstract: A semiconductor device for driving a load of an object includes a differential circuit receiving an input signal and outputting differential output signals, first to fourth output circuits receiving the differential output signals, and a control circuit configured to respectively connect or disconnect the differential circuit to each of the first to fourth output circuits. The first output circuit is connected between high-level and mid-level power supply terminals and outputs a first output signal to the differential circuit, the second output circuit is connected between the high-level and mid-level power supply terminals, and outputs a second output signal to the load, a third output circuit is connected between mid-level and low-level power supply terminals, and outputs a third output signal to the differential circuit, and a fourth output circuit is connected between the mid-level low-level power supply terminals, and outputs a fourth output signal to the load.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: March 31, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Kenichi Shiibayashi
  • Patent number: 10559248
    Abstract: A display apparatus includes: a display panel; a gate driver that provides, to a plurality of scanning lines, scanning pulse signals for controlling pixel switches to be ON in a selection period corresponding to a pulse width thereof; a data driver that provides gradation voltage signals to a plurality of data lines; and a display controller that provides a modulated clock signal having a frequency that changes at a predetermined rate in one frame period. The gate driver sequentially provides the scanning pulse signals each having a pulse width reflecting to a clock cycle of the modulated clock signal in a predetermined order corresponding to distances from the data driver to the plurality of scanning lines. The data driver provides the gradation voltage signals in the order of providing the scanning pulse signals for every data period corresponding to the clock cycle of the modulated clock signal.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: February 11, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventors: Hiroshi Tsuchi, Katsunori Ito
  • Publication number: 20190221153
    Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.
    Type: Application
    Filed: March 28, 2019
    Publication date: July 18, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi TSUCHI, Manabu NISHIMIZU, Yuushi SYUTOU
  • Publication number: 20190147825
    Abstract: A differential amplifier circuit includes a differential input stage, a first current mirror, a second current mirror, a first current source circuit, and a second current source circuit. The first current source circuit has a first transistor of a first conductivity type with a control terminal supplied with a first bias voltage, and a second transistor of a second conductivity type with a control terminal supplied with a second bias voltage. An output amplifier circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. A control circuit has a fifth transistor of the first conductivity type with a first terminal connected to a connection point between the other end of the second current source circuit and the control terminal of the fourth transistor in the output amplifier circuit, with a second terminal connected to an output node of the second current mirror, and with a control terminal receiving the first bias voltage.
    Type: Application
    Filed: January 9, 2019
    Publication date: May 16, 2019
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi TSUCHI
  • Patent number: 10262575
    Abstract: A current corresponding to the difference between an input signal voltage and an output signal voltage is generated as an amplification acceleration current. The amplification acceleration current is sent to an output node of a current mirror, which drives a transistor in an output amplifier stage, and therefore added to a current to drive the transistor in the output amplifier stage.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: April 16, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi Tsuchi, Manabu Nishimizu, Yuushi Syutou
  • Patent number: 10255847
    Abstract: A level shift circuit is configured to receive reference voltage and first to third voltages, and to generate an output signal. The voltages satisfy a condition in which the reference voltage<the first voltage<the second voltage<the third voltage or the reference voltage>the first voltage>the second voltage>the third voltage. The level shift circuit includes a first level shift circuit configured to receive a first signal having a first amplitude within a difference between the reference and first voltages, and level shift the first signal to a second signal having a second amplitude within a difference between the reference and second voltages, and a second level shift circuit configured to level shift the second signal to a third signal having a third amplitude within a difference between the reference and third voltages, and output the third signal as the output signal.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: April 9, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi Tsuchi
  • Patent number: 10210838
    Abstract: A level shift circuit includes first and second NMOS transistors that are coupled between a first supply terminal, and first and second output nodes, respectively, and have respective control terminals receiving input signals of a low amplitude, third and fourth PMOS transistors which are coupled between a second supply terminal, and the first and second output nodes outputting signals of high amplitude, respectively, a fifth PMOS transistor which is coupled between a gate of the third PMOS transistor and the second output node, and has a gate coupled to the first output node, a sixth PMOS transistor which is coupled between a gate of the fourth PMOS transistor and the first output node, and has a gate coupled to the second output node, and first and second load elements which are coupled between the second supply terminal and the gates of the third and fourth PMOS transistors, respectively.
    Type: Grant
    Filed: July 7, 2017
    Date of Patent: February 19, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Hiroshi Tsuchi
  • Patent number: 10199007
    Abstract: A differential amplifier circuit includes a differential input stage, a first current mirror, a second current mirror, a first current source circuit, and a second current source circuit. The first current source circuit has a first transistor of a first conductivity type with a control terminal supplied with a first bias voltage, and a second transistor of a second conductivity type with a control terminal supplied with a second bias voltage. An output amplifier circuit includes a third transistor of the first conductivity type and a fourth transistor of the second conductivity type. A control circuit has a fifth transistor of the first conductivity type with a first terminal connected to a connection point between the other end of the second current source circuit and the control terminal of the fourth transistor in the output amplifier circuit, with a second terminal connected to an output node of the second current mirror, and with a control terminal receiving the first bias voltage.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 5, 2019
    Assignee: LAPIS Semiconductor Co., Ltd.
    Inventor: Hiroshi Tsuchi
  • Publication number: 20180336862
    Abstract: A semiconductor device for driving a load of an object includes a differential circuit receiving an input signal and outputting differential output signals, first to fourth output circuits receiving the differential output signals, and a control circuit configured to respectively connect or disconnect the differential circuit to each of the first to fourth output circuits. The first output circuit is connected between high-level and mid-level power supply terminals and outputs a first output signal to the differential circuit, the second output circuit is connected between the high-level and mid-level power supply terminals, and outputs a second output signal to the load, a third output circuit is connected between mid-level and low-level power supply terminals, and outputs a third output signal to the differential circuit, and a fourth output circuit is connected between the mid-level low-level power supply terminals, and outputs a fourth output signal to the load.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 22, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi TSUCHI, Kenichi SHIIBAYASHI
  • Publication number: 20180330655
    Abstract: A display apparatus includes: a display panel; a gate driver that provides, to a plurality of scanning lines, scanning pulse signals for controlling pixel switches to be ON in a selection period corresponding to a pulse width thereof; a data driver that provides gradation voltage signals to a plurality of data lines; and a display controller that provides a modulated clock signal having a frequency that changes at a predetermined rate in one frame period. The gate driver sequentially provides the scanning pulse signals each having a pulse width reflecting to a clock cycle of the modulated clock signal in a predetermined order corresponding to distances from the data driver to the plurality of scanning lines. The data driver provides the gradation voltage signals in the order of providing the scanning pulse signals for every data period corresponding to the clock cycle of the modulated clock signal.
    Type: Application
    Filed: March 7, 2018
    Publication date: November 15, 2018
    Applicant: LAPIS Semiconductor Co., Ltd.
    Inventors: Hiroshi TSUCHI, Katsunori ITO
  • Publication number: 20180301079
    Abstract: An output circuit includes: a differential amplifier including inverting input terminal, non-inverting input terminals and output terminal, and outputs, form the output terminal, a voltage having a level corresponding to a weighted average of respective input voltage levels of the non-inverting input terminals, when the output voltage level is equal to a input voltage level of the inverting input terminal, and outputs a voltage having a level corresponding to a difference between a level corresponding to a weighted average of the respective input voltage levels of the non-inverting input terminals and the input voltage level, when which the output voltage level is different from the input voltage level; and a delay circuit that generates a delay voltage responding with a predetermined time constant with respect to a change in the output voltage level and supplies the delay voltage to the inverting input terminal.
    Type: Application
    Filed: April 16, 2018
    Publication date: October 18, 2018
    Inventors: HIROSHI TSUCHI, TAKESHI NOSAKA, KOJI HIGUCHI