Patents by Inventor Hiroshi Yanagimoto
Hiroshi Yanagimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240229280Abstract: A mask structure includes a screen mask having a penetrating portion with a predetermined pattern. The screen mask includes a mesh portion having an opening formed in a grid pattern, and a mask portion having the penetrating portion and being fixed to the mesh portion so as to face the substrate. The mask portion includes a core portion that retains the shape of the mask portion, and a seal portion made of an elastic material softer than the material of the core portion and contacting the substrate.Type: ApplicationFiled: October 4, 2023Publication date: July 11, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki KONDOH, Keiji KURODA, Koji INAGAKI, Kazuaki OKAMOTO, Hiroshi YANAGIMOTO
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Patent number: 12028989Abstract: Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.Type: GrantFiled: June 13, 2022Date of Patent: July 2, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kazuaki Okamoto, Hiroshi Yanagimoto, Rentaro Mori
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Publication number: 20240133070Abstract: A mask structure includes a screen mask having a penetrating portion with a predetermined pattern. The screen mask includes a mesh portion having an opening formed in a grid pattern, and a mask portion having the penetrating portion and being fixed to the mesh portion so as to face the substrate. The mask portion includes a core portion that retains the shape of the mask portion, and a seal portion made of an elastic material softer than the material of the core portion and contacting the substrate.Type: ApplicationFiled: October 3, 2023Publication date: April 25, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki KONDOH, Keiji KURODA, Koji INAGAKI, Kazuaki OKAMOTO, Hiroshi YANAGIMOTO
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Patent number: 11903141Abstract: A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.Type: GrantFiled: August 12, 2021Date of Patent: February 13, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keiji Kuroda, Rentaro Mori, Hiroshi Yanagimoto, Haruki Kondoh, Kazuaki Okamoto, Akira Kato
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Patent number: 11785721Abstract: First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.Type: GrantFiled: February 15, 2022Date of Patent: October 10, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki Kondoh, Rentaro Mori, Keiji Kuroda, Kazuaki Okamoto, Akira Kato, Jyunya Murai, Hiroshi Yanagimoto, Kenji Nakamura, Tomoya Okazaki
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Publication number: 20230302578Abstract: Provided is a method for manufacturing a board with a roughened surface and a method for manufacturing a board having a plated layer that allow easily manufacturing the board having a plated layer. One of embodiments is a method for manufacturing a board with a surface roughened for wiring formation. The method for manufacturing a board includes performing laser ablation on a board containing a resin at least on a surface of the board. A laser light irradiated in the laser ablation is a laser light having a pulse width of 1 ps or less, a wavelength of 320 nm or more, and an output of 1 W or less.Type: ApplicationFiled: January 26, 2023Publication date: September 28, 2023Inventors: Hiroshi YANAGIMOTO, Oji KUNO, Jyunya MURAI, Keiji KURODA, Tomoya OKAZAKI, Rentaro MORI
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Patent number: 11700686Abstract: A method for manufacturing a wiring board capable of improving adhesion between an underlayer and a seed layer. An electrically conductive underlayer is disposed on the surface of an insulating substrate and a seed layer containing metal is disposed on the surface of the underlayer to prepare a substrate with seed-layer. A diffusion layer in which elements forming the underlayer and seed layer are mutually diffused is formed between the underlayer and the seed layer, by irradiating the seed layer with a laser beam. A metal layer is formed on the surface of the seed layer by disposing a solid electrolyte membrane between an anode and the seed layer as a cathode and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from the insulating substrate.Type: GrantFiled: July 2, 2021Date of Patent: July 11, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keiji Kuroda, Haruki Kondoh, Kazuaki Okamoto, Rentaro Mori, Hiroshi Yanagimoto
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Patent number: 11696410Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.Type: GrantFiled: May 19, 2021Date of Patent: July 4, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki Kondoh, Rentaro Mori, Hiroshi Yanagimoto, Keiji Kuroda, Kazuaki Okamoto
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Patent number: 11665829Abstract: A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.Type: GrantFiled: December 15, 2020Date of Patent: May 30, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki Kondoh, Rentaro Mori, Keiji Kuroda, Hiroshi Yanagimoto, Kazuaki Okamoto
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Patent number: 11490528Abstract: Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.Type: GrantFiled: September 11, 2020Date of Patent: November 1, 2022Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Kazuaki Okamoto, Hiroshi Yanagimoto, Rentaro Mori
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Publication number: 20220304162Abstract: Provided is a method for manufacturing a wiring board that forms a wiring layer having favorable adhesion without a resin resist pattern. A method prepares a substrate with seed-layer including: a underlayer on the surface of an insulating substrate; and a seed layer on the surface of the underlayer, the seed layer having a predetermined pattern and containing metal; presses a solid electrolyte membrane against the seed layer and the underlayer, and applies voltage between an anode and the underlayer to reduce metal ions in the membrane and form a metal layer on the surface of the seed layer; and removes an exposed region without the seed layer and the metal layer of the underlayer to form a wiring layer including the underlayer, the seed layer and the metal layer on the surface of the substrate.Type: ApplicationFiled: June 13, 2022Publication date: September 22, 2022Inventors: Kazuaki OKAMOTO, Hiroshi YANAGIMOTO, Rentaro MORI
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Publication number: 20220272847Abstract: First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.Type: ApplicationFiled: February 15, 2022Publication date: August 25, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki KONDOH, Rentaro MORI, Keiji KURODA, Kazuaki OKAMOTO, Akira KATO, Jyunya MURAI, Hiroshi YANAGIMOTO, Kenji NAKAMURA, Tomoya OKAZAKI
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Patent number: 11425823Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate including an insulation substrate, a conductive undercoat layer, and a conductive seed layer provided in a first region, in that order, is first prepared. An insulation layer covering the seed layer and the undercoat layer is then formed. Subsequently, the insulation layer is etched to expose a surface of the seed layer and form a remaining insulation layer covering the undercoat layer in the second region. Subsequently, a voltage is applied between an anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing aqueous solution disposed between the seed layer and the anode and the membrane and the seed layer pressed into contact with each other, thereby a metal layer being formed on the surface of the seed layer. Thereafter, the remaining insulation layer is removed and the undercoat layer is etched.Type: GrantFiled: June 4, 2021Date of Patent: August 23, 2022Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki Kondoh, Rentaro Mori, Hiroshi Yanagimoto, Keiji Kuroda, Kazuaki Okamoto
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Patent number: 11425824Abstract: A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.Type: GrantFiled: June 14, 2021Date of Patent: August 23, 2022Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keiji Kuroda, Haruki Kondoh, Kazuaki Okamoto, Rentaro Mori, Hiroshi Yanagimoto
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Publication number: 20220061165Abstract: A method for manufacturing a wiring board in which the adhesion between an underlayer and a seed layer is improved. A diffusion layer in which an element forming the underlayer and an element forming a coating layer are mutually diffused is formed between the underlayer and a wiring portion of the coating layer by irradiating the wiring portion with a laser beam. A seed layer is formed by removing a portion excluding the wiring portion of the coating layer from the underlayer. A metal layer is formed by disposing a solid electrolyte membrane between an anode and the seed layer and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from an insulating substrate.Type: ApplicationFiled: August 12, 2021Publication date: February 24, 2022Inventors: Keiji KURODA, Rentaro MORI, Hiroshi YANAGIMOTO, Haruki KONDOH, Kazuaki OKAMOTO, Akira KATO
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Publication number: 20220007506Abstract: A method for manufacturing a wiring board capable of improving adhesion between an underlayer and a seed layer. An electrically conductive underlayer is disposed on the surface of an insulating substrate and a seed layer containing metal is disposed on the surface of the underlayer to prepare a substrate with seed-layer. A diffusion layer in which elements forming the underlayer and seed layer are mutually diffused is formed between the underlayer and the seed layer, by irradiating the seed layer with a laser beam. A metal layer is formed on the surface of the seed layer by disposing a solid electrolyte membrane between an anode and the seed layer as a cathode and applying voltage between the anode and the underlayer. An exposed portion without the seed layer of the underlayer is removed from the insulating substrate.Type: ApplicationFiled: July 2, 2021Publication date: January 6, 2022Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keiji KURODA, Haruki KONDOH, Kazuaki OKAMOTO, Rentaro MORI, Hiroshi YANAGIMOTO
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Publication number: 20210410291Abstract: A seeded substrate is first prepared. The seeded substrate includes an insulation substrate having a main surface composed of a first region and a second region other than the first region, and a conductive seed layer provided on the first region. Subsequently, a conductive layer is formed on at least the second region to obtain a first treated substrate. An insulation layer is then formed on the first treated substrate. The seed layer is then exposed. A metal layer is then formed on the surface of the seed layer. Here, a voltage is applied between the anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing solution being disposed between the second treated substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the insulation layer and the conductive layer are removed.Type: ApplicationFiled: June 14, 2021Publication date: December 30, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keiji KURODA, Haruki KONDOH, Kazuaki OKAMOTO, Rentaro MORI, Hiroshi YANAGIMOTO
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Publication number: 20210392753Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate including an insulation substrate, a conductive undercoat layer, and a conductive seed layer provided in a first region, in that order, is first prepared. An insulation layer covering the seed layer and the undercoat layer is then formed. Subsequently, the insulation layer is etched to expose a surface of the seed layer and form a remaining insulation layer covering the undercoat layer in the second region. Subsequently, a voltage is applied between an anode and the seed layer while a solid electrolyte membrane containing a metal ion-containing aqueous solution disposed between the seed layer and the anode and the membrane and the seed layer pressed into contact with each other, thereby a metal layer being formed on the surface of the seed layer. Thereafter, the remaining insulation layer is removed and the undercoat layer is etched.Type: ApplicationFiled: June 4, 2021Publication date: December 16, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki KONDOH, Rentaro MORI, Hiroshi YANAGIMOTO, Keiji KURODA, Kazuaki OKAMOTO
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Publication number: 20210378103Abstract: The present disclosure provides a method for producing a wiring substrate. A seeded substrate is first prepared. The seeded substrate includes an insulation substrate, a conductive undercoat layer having a hydrophilic surface and provided on the insulation substrate, a conductive seed layer provided on a first region of the surface of the undercoat layer, the first region having a predetermined pattern, and a water-repellent layer on the second region of the surface of the undercoat layer, the second region being a region other than the first region. Subsequently, a metal layer is formed on the seed layer. A voltage is applied between the anode and the seed layer while a solid electrolyte membrane being disposed between the seeded substrate and the anode, and the solid electrolyte membrane and the seed layer being pressed into contact with each other. Thereafter, the water-repellent layer and the undercoat layer are etched.Type: ApplicationFiled: May 19, 2021Publication date: December 2, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki KONDOH, Rentaro MORI, Hiroshi YANAGIMOTO, Keiji KURODA, Kazuaki OKAMOTO
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Publication number: 20210204409Abstract: A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.Type: ApplicationFiled: December 15, 2020Publication date: July 1, 2021Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Haruki KONDOH, Rentaro MORI, Keiji KURODA, Hiroshi YANAGIMOTO, Kazuaki OKAMOTO