Patents by Inventor Hirotaka Kato

Hirotaka Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5897743
    Abstract: A peeling jig is provided for peeling a bonded wafer having voids formed in bonding surfaces so as to rebond, which does not injure the bonding surfaces or cause the adherence of particles thereto. The peeling jig includes a wedge portion 1a for inserting into the bonding surfaces, and a flat portion provided at the both sides of the base of the wedge portion. The apex angle of the wedge portion, when the chamfered angles at the bonding sides of the supporting substrate and active wafer of the bonded wafer to be separated are respectively .alpha. and .beta., is .theta. and .theta.>.alpha.+.beta.. When the wedge portion is inserted into the bonding surfaces, the right and left inclined surfaces of the wedge portion are in contact with the peripheries of the chamfered portions, and then chamfered portions are flared.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: April 27, 1999
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kazuaki Fujimoto, Hiroshi Furukawa, Hirotaka Kato
  • Patent number: 5849603
    Abstract: A surface processing method for evaluating semiconductor substrate is intended to clean a semiconductor substrate, which has the surface of a silicon layer exposed by removing the epitaxial layer by an acid mixture, by buffered HF and then to perform SC-1 cleaning. Placing the substrate for about 2 hours after the processing, then the varying rate of the SPV value is quite stable at about 5%, so that the minor carrier diffusion length can be measured with high precision. Furthermore, the lead time of evaluating a semiconductor substrate can be significantly reduced over the prior-art method.
    Type: Grant
    Filed: April 2, 1996
    Date of Patent: December 15, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirotaka Kato, Yuji Sato, Kei Matsumoto
  • Patent number: 5770511
    Abstract: The present invention, a silicon-on-insulator (SOI) substrate and its fabrication method, is suited to the wafer-bonding method. A pre-oxidation treatment accompanying the oxidation treatment and the adhesive thermal treatment to prevent metal impurities from polluting semiconductor wafers. Before an oxide layer is thermally grown on one wafer or after two bonded wafers are subjected to a adhesive thermal treatment at a temperature T1, the pre-oxidation treatment is performed at a temperature of T2, which satisfies the relation equation of T1-300.ltoreq.T2.ltoreq.T1-100 (.degree.C.). Water steam, pure oxygen, or diluted oxygen, is conducted into the furnace, in which the pre-oxidation treatment is performed in an oxidation ambient. Accordingly, an oxide film having a predetermined thickness is formed on the surface of the SOI substrate serving as a barrier for preventing metal impurities, such as Fe, Cr, or the like, from invading the substrate and degrading the electrical characteristics thereof.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: June 23, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Kei Matsumoto, Hirotaka Kato, Hiroshi Furukawa
  • Patent number: 5742176
    Abstract: An evaluation method of a silicon wafer by correctly calculating the Fe--B concentration is disclosed. Even when the SPV method is utilized, the over-estimated Fe--B concentration in silicon wafers containing oxygen-precipitation defects can be avoided. Diffusion lengths Lb and La of minority carriers in a P-type silicon wafer before and after an activation step are measured by the SPV method. A value of (Lb--La)/Lb calculated from La and Lb is compared with a constant C which is read from the plot of Lb vs. (Lb--La). If (Lb--La)/Lb is smaller than constant C, the concentration calculation is terminated since there are oxygen-precipitation defects in the silicon wafer. The calculation is carried out for silicon wafers containing no oxygen-precipitation defects, and is based on the formula of Fe--B concentration (cm.sup.-3).apprxeq.1.times.10.sup.16 (La.sup.-2 --Lb.sup.-2).
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: April 21, 1998
    Assignee: Komatsu Electronic Metals Co., Ltd.
    Inventors: Hirotaka Kato, Kei Matsumoto
  • Patent number: 5742175
    Abstract: An evaluation method to efficiently and precisely measure high-density oxygen-precipitation defects in the bulk of a silicon wafer is disclosed. A number of silicon wafers containing oxygen-precipitation defects are provided. The SPV method is utilized to measure the diffusion length of the minority carriers in the silicon wafers. The density of oxygen-precipitation defects is measured by the infrared tomography method. The diffusion length and the defect density are plotted and are found to be correlated. That is, the SPV measured diffusion length of the minority carriers and the defect density obtained by the infrared tomography method have specific relationships. A constant A can then be obtained from the plot. The diffusion length L of minority carriers in silicon wafers provided for evaluation is measured by the SPV method. Finally, the bulk oxygen-precipitation defects density can be calculated from the formula A.times.L.sup.-2.
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: April 21, 1998
    Assignee: Komatsu Electronic Metals, Inc.
    Inventors: Hirotaka Kato, Kei Matsumoto