Abstract: A display device is mounted on a vehicle. The display device comprises a display unit and a control unit A virtual screen is a two-dimensional plane at a predetermined distance away from an origin of a XYZ coordinate system along a Y coordinate axis, and is approximately parallel to an XZ plane defined by an X coordinate axis and a Z coordinate axis. The control unit is configured to calculate coordinates of a second point obtained as a result of projecting a first point in the XYZ coordinate system onto the virtual screen, convert the calculated coordinates of the second point into coordinates according to a display mode of the display unit, and cause the display unit to display an image corresponding to the second point at the converted coordinates.

Abstract: A display device is mounted on a vehicle. The display device comprises a display unit and a control unit A virtual screen is a two-dimensional plane at a predetermined distance away from an origin of a XYZ coordinate system along a Y coordinate axis, and is approximately parallel to an XZ plane defined by an X coordinate axis and a Z coordinate axis. The control unit is configured to calculate coordinates of a second point obtained as a result of projecting a first point in the XYZ coordinate system onto the virtual screen, convert the calculated coordinates of the second point into coordinates according to a display mode of the display unit, and cause the display unit to display an image corresponding to the second point at the converted coordinates.

Abstract: An image processing linkage system includes: an image processing apparatus and a portable terminal device connectable with each other, wherein the image processing apparatus includes a display unit, and a transmitting unit, the portable terminal device includes a display unit, a receiving unit, a display control unit, an operation information converting unit, and a transmitting unit, and the image processing apparatus receives the operation information transmitted from the portable terminal device, and executes a process corresponding to the operation information.

Abstract: An allocation apparatus configured to allocate a plurality of information processing devices to two or more management apparatuses that perform distributed management of the plurality of information processing devices, the allocation apparatus includes: an allocation unit configured to allocate an address range on a network, allocatable to a plurality of information processing devices, to the two or more management apparatuses; and an acquisition unit configured to obtain, from each of the two or more management apparatuses, management information indicating a state of the information processing device whose address belongs to a range allocated to the management apparatus, wherein the allocation unit dynamically performs allocation of the address range on the network based on the management information that has been obtained by the acquisition unit.

Abstract: An amplifier circuit includes a sampling circuit and an amplifier connected to an output of the sampling circuit. A feedback capacitor is between an output terminal of the amplifier and an output terminal of the sampling circuit. A quantizer that includes a comparator is configured to quantize a voltage at the output terminal of the sampling circuit according to a comparison of a voltage at the output terminal of the sampling circuit to a voltage at the reference potential terminal of the comparator. The quantizer outputs a digital code according to the voltage comparison. A control circuit receives the digital code from the quantizer and stores the digital code in a register as a cancellation digital code. A digital-analog (D/A) converter outputs an analog signal in accordance with digital codes from the control circuit.

Abstract: A switched capacitor circuit includes a first sampling circuit having a first sampling capacitance element. The first sampling circuit receives an input voltage and outputs a sampled voltage according to a first sampling operation. A quantizer quantizes the sampled voltage output from the first sampling circuit and outputs a quantized value corresponding to the sampled voltage. A digital-to-analog converter outputs an analog signal in accordance with the quantized value from the quantizer. A first logic circuit outputs an instruction to start a sampling operation of a second sampling circuit, which is configured to sample the analog signal output from the digital-to-analog converter, when the quantizer completes quantization of the sampled voltage.

Abstract: According to one embodiment, an amplification circuit includes a differential amplifier and a feedback circuit. The differential amplifier includes a sampling circuit that samples a first voltage which is a difference between an adjustment voltage supplied to a first terminal and a first input voltage, and a second voltage which is a difference between the adjustment voltage and a second input voltage. The differential amplifier amplifies the first voltage to output a first voltage signal and amplifies the second voltage to output a second voltage signal. The feedback circuit detects a common mode voltage of the first voltage signal and the second voltage signal, and adjusts the adjustment voltage which is supplied to the first terminal in accordance with the common mode voltage.

Abstract: According to one embodiment, a first AD converter converts a first voltage into a first digital signal. A voltage/time conversion circuit acquires a residual corresponding to a difference between the first voltage and a result of having converted the first digital signal into an analog signal and converts the residual into a time signal according to a voltage in a first capacitor. A time/voltage conversion circuit converts the time signal into a voltage signal according to a voltage in a second capacitor. A second AD converter converts the voltage signal into a second digital signal. A digital processing circuit outputs a third digital signal to adjust a current value of first or the second current sources based on the second digital signal.

Abstract: According to one embodiment, an amplification circuit includes a differential amplifier and a feedback circuit. The differential amplifier includes a sampling circuit that samples a first voltage which is a difference between an adjustment voltage supplied to a first terminal and a first input voltage, and a second voltage which is a difference between the adjustment voltage and a second input voltage. The differential amplifier amplifies the first voltage to output a first voltage signal and amplifies the second voltage to output a second voltage signal. The feedback circuit detects a common mode voltage of the first voltage signal and the second voltage signal, and adjusts the adjustment voltage which is supplied to the first terminal in accordance with the common mode voltage.

Abstract: According to one embodiment, a first AD converter converts a first voltage into a first digital signal. A voltage/time conversion circuit acquires a residual corresponding to a difference between the first voltage and a result of having converted the first digital signal into an analog signal and converts the residual into a time signal according to a voltage in a first capacitor. A time/voltage conversion circuit converts the time signal into a voltage signal according to a voltage in a second capacitor. A second AD converter converts the voltage signal into a second digital signal. A digital processing circuit outputs a third digital signal to adjust a current value of first or the second current sources based on the second digital signal.

Abstract: According to one embodiment, an amplifier circuit includes a first converter generating a time signal by voltage-time converting an input signal; a second converter generating an output signal by time-voltage converting the time signal; and a correction circuit outputting a control signal by comparing the time signal and a reference signal. The first converter generates the time signal, based on the control signal.

Abstract: An allocation apparatus configured to allocate a plurality of information processing devices to two or more management apparatuses that perform distributed management of the plurality of information processing devices, the allocation apparatus includes: an allocation unit configured to allocate an address range on a network, allocatable to a plurality of information processing devices, to the two or more management apparatuses; and an acquisition unit configured to obtain, from each of the two or more management apparatuses, management information indicating a state of the information processing device whose address belongs to a range allocated to the management apparatus, wherein the allocation unit dynamically performs allocation of the address range on the network based on the management information that has been obtained by the acquisition unit.

Abstract: An image processing linkage system includes: an image processing apparatus and a portable terminal device connectable with each other, wherein the image processing apparatus includes a display unit, and a transmitting unit, the portable terminal device includes a display unit, a receiving unit, a display control unit, an operation information converting unit, and a transmitting unit, and the image processing apparatus receives the operation information transmitted from the portable terminal device, and executes a process corresponding to the operation information.

Abstract: According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator.

Abstract: An A/D converter includes a plurality of AD converting sections that sequentially operate at predetermined intervals. The AD converting section has an ADC that converts an analog signal into a digital signal and outputs the digital signal, a memory that stores, as a specific polarity value, the polarity of a signal obtained by the ADC digitizing an analog signal at a reference voltage, an analog polarity converting circuit that inverts the polarity of the analog signal based on the specific polarity value and a set polarity value, which is previously set, and a digital polarity converting circuit that inverts the polarity of the digital signal based on the specific polarity value and the set polarity value.

Abstract: An A/D converter includes a plurality of AD converting sections that sequentially operate at predetermined intervals. The AD converting section has an ADC that converts an analog signal into a digital signal and outputs the digital signal, a memory that stores, as a specific polarity value, the polarity of a signal obtained by the ADC digitizing an analog signal at a reference voltage, an analog polarity converting circuit that inverts the polarity of the analog signal based on the specific polarity value and a set polarity value, which is previously set, and a digital polarity converting circuit that inverts the polarity of the digital signal based on the specific polarity value and the set polarity value.

Abstract: A successive-approximation A/D converter includes a reference voltage generator configured to generate a reference voltage, a comparator configured to receive an input analog signal and generate a voltage difference by comparing the input analog signal and the reference voltage, an error-correction circuit including a variable capacitor configured to correct the voltage difference based on a capacitance of the variable capacitor, an error-correction controller configured to retrieve from memory a correction amount and control the error-correction circuit to vary the capacitance of the variable capacitor according to the correction amount, and a successive approximation register logic circuit configured to generate an output digital signal based on the voltage difference from the comparator.

Abstract: According to the present invention, a successive approximation type analog-digital converter includes: a comparator outputting a result of comparing an analog signal and a reference voltage; a register storing a digital value corresponding to the result of comparison and outputting a digital signal; a detection unit detecting whether the comparator is in a stable state or not for each bit; and a bit determination unit storing, if the comparator is not stable, as a bit value of a bit which is one bit lower-order than a corresponding detection bit, a value obtained by inverting a final determined bit value of the detection bit in the register instead of the comparison result of the comparator.

Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.