Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N?1 first residual signal according to a difference between the first difference signal and 2N?1?1 first reference signal, the 2N?1?1 first reference signal being 2N?1?1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N?1 first residual signal with a fixed voltage to obtain 2N?1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N?1 first comparison signal to obtain first data of N bits.

Abstract: A successive-approximation A/D converter includes a reference voltage generator configured to generate a reference voltage, a comparator configured to receive an input analog signal and generate a voltage difference by comparing the input analog signal and the reference voltage, an error-correction circuit including a variable capacitor configured to correct the voltage difference based on a capacitance of the variable capacitor, an error-correction controller configured to retrieve from memory a correction amount and control the error-correction circuit to vary the capacitance of the variable capacitor according to the correction amount, and a successive approximation register logic circuit configured to generate an output digital signal based on the voltage difference from the comparator.

Abstract: According to an embodiment, there are provided a capacitor DAC for generating an output signal in accordance with a connection state of a capacitor element, a reference voltage generation circuit for supplying a reference voltage to the capacitor DAC, a comparator for outputting a comparison result in accordance with the output signal, a successive approximation register for outputting a digital signal in accordance with the comparison result, and a control circuit for controlling a connection state of the capacitor element in accordance with the comparison result and comparing an ideal code with a digital signal obtained by sampling a predetermined voltage, thereby correcting an error of the digital signal.

Abstract: There is provided with a residual signal generating circuit in which the capacitive DA converter generates a first difference signal with respect to an input signal based on a criterion voltage, the criterion voltage being indicative of an input range of the input signal, the reference voltage generating circuit divides the criterion voltage to obtain at least one partial voltage signal, the residual signal generating section generates 2N?1 first residual signal according to a difference between the first difference signal and 2N?1?1 first reference signal, the 2N?1?1 first reference signal being 2N?1?1 partial voltage signal among said at least one partial voltage signal generated by the reference voltage generating circuit, the comparator compares the 2N?1 first residual signal with a fixed voltage to obtain 2N?1 first comparison signal each indicative of a logical value, and the decoder decodes the 2N?1 first comparison signal to obtain first data of N bits.

Abstract: A pipelined A/D converter circuit includes a sample hold circuit configured to sample and hold an analog input signal, and output a sample hold signal, and an A/D converter circuit including A/D converter circuit parts connected to each other in cascade, and performs A/D conversion in a pipelined form. The pipelined A/D converter circuit part of each stage includes a sub-A/D converter circuit, a multiplier D/A converter circuit, and a precharge circuit. The sub-A/D converter circuit includes comparators, and A/D convert the input signal into a digital signal of predetermined bits, a multiplier D/A converter circuit for D/A converting the digital signal from the sub-A/D converter circuit into an analog control signal generated with a reference voltage served as a reference value, sample, hold and amplify the input signal by sampling capacitors based on the analog control signal.

Abstract: An arithmetic circuit includes: an input terminal for receiving an input signal; plural capacitors; and an amplifier circuit including an amplifying input terminal and an output terminal and configured to amplify a signal input from the amplifying input terminal and output it as an output signal from the output terminal. A first switch circuit becomes conductive based on a first control signal and connects the plural capacitors in parallel between the input terminal and a first voltage terminal for supplying a first voltage. A second switch circuit becomes conductive based on a second control signal and connects a first capacitor of the plural capacitors between the amplifying input terminal and a second voltage terminal for supplying a second voltage to form a first current path and a second capacitor of the plural capacitors between the amplifying input terminal and the output terminal to form a second current path.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: A semiconductor integrated circuit includes a first and second power supply domain circuits having a first and second power supply terminals, respectively. An internal signal propagation line propagates a signal from a circuit of the first power supply domain circuit to that of the second power supply domain circuit. A voltage detector detects a surge voltage input to the first and second power supply terminals and outputs, from a control signal node, a control signal which is determined in accordance with a capacitive coupling by a first capacitor between the first power supply terminal and the control signal node, a second capacitor between the second power supply terminal and the control signal node, and a load capacitance at an output side of the control signal node. A voltage limiting circuit limits a voltage of a signal on the internal signal propagation line in accordance with the control signal.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.

Abstract: Certain embodiments provide an electronic circuit and a correction circuit. The electronic circuit includes a plurality of semiconductor elements. The correction circuit controls voltage of the semiconductor elements such that a difference between electric characteristics of the semiconductor elements autonomously decreases.

Abstract: In order to carry out an image processing with high precision by using a simple structure, an image processing apparatus is provided with an input unit, a storage unit, a binarization unit, and a determination unit. The input unit inputs image data of an image. The storage unit stores a first condition on absolute positions of pixels in the image and a second condition on positions of pixels relative to a target pixel. The binarization unit binarizes the target pixel based upon a color data of the target pixel and that of at least one related pixel to the target pixel to generate a binarized value. The at least one related pixel in the image satisfies the first and second conditions. The determination unit determines whether or not the image has a specified pattern, based upon the binarized values.

Abstract: In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.

Abstract: In order to carry out an image processing with high precision by using a simple structure, an image processing apparatus is provided with an input unit, a storage unit, a binarization unit, and a determination unit. The input unit inputs image data of an image. The storage unit stores a first condition on absolute positions of pixels in the image and a second condition on positions of pixels relative to a target pixel. The binarization unit binarizes the target pixel based upon a color data of the target pixel and that of at least one related pixel to the target pixel to generate a binarized value. The at least one related pixel in the image satisfies the first and second conditions. The determination unit determines whether or not the image has a specified pattern, based upon the binarized values.

Abstract: To reduce a random noise power included in an analog input signal, a discrete-time circuit samples an inputted analog signal a plurality of number of times at different times respectively and performs averaging processing on sampling results, thus enabling to respond appropriately even if an input signal has a high frequency without increasing a size of the circuit.

Abstract: In a network printing system, initial print setting information and save-mode print setting information are preparatorily set as print setting information in a server. In response to a request from PC1 or PC2, the server sends the save-mode print setting information as the “print setting information” if the total number of print copies exceeds a predetermined number. If a user does not agree with the save-mode print setting information displayed on the PC1 or PC2, the user operates a button “no” in a confirmation dialogue and then resets the print setting information. A printing apparatus performs save-mode printing or normal printing in accordance with the set or reset print setting information. Therefore, an administrator of the network printing system has only to set the initial print setting information and the save-mode print setting information in the server. Thus, the network printing system allows print setting to be simply achieved.

Abstract: To provide a common-mode feedback circuit that feeds back signal corresponding to common-mode components of output terminal voltage of first and second amplifiers to input terminals of the first and second amplifiers via first and second passive elements connected to a common terminal, respectively.

Abstract: In an A/D converter, three capacitors are connected to a comparator. The A/D converter also includes three switching circuits that each input a first reference voltage, a second reference voltage, and a third reference voltage in the three capacitors. A control circuit selects at least two of the three switching circuits during a charging period of stray capacitance of each of the capacitors. The control circuit turns on one of the switching devices in the selected switching circuits simultaneously, and during a comparing period by the comparator, selects one of the three capacitors for each comparison, and selects another capacitor in the next comparison.

Abstract: In order to limit the range of externally outputable content of externally input speech, an MFP includes: a speech acquiring portion to acquire externally input speech; a speech converting portion to convert the acquired speech into character information; a user extracting portion to extract user identification information for identifying a user from the character information; and an output control portion to output the character information based on the extracted user identification information.