Patents by Inventor Hirotomo Ishii

Hirotomo Ishii has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030095276
    Abstract: In an image processor, a memory device stores output inhibition conditions for inhibiting print of an image including a specified pattern. The input image data is converted to first image data for image forming. On the other hand, the input image data is also converted to second image data in correspondence to a state of a print obtained by the image output device, and a detector detects the specified pattern in the second image data based on the output inhibition conditions. Alternatively, a converter converts the output inhibition conditions to detection parameters according to output characteristics of the image output device, and a detector detects the specified pattern in the input image data based on the detection parameters. Then, a controller controls the output of the processed image data according to a result of the detection.
    Type: Application
    Filed: June 14, 2001
    Publication date: May 22, 2003
    Inventors: Naoka Hiramatsu, Hirotomo Ishii, Akira Murakawa
  • Publication number: 20030095277
    Abstract: A print system has an image processor which processes data and a printer which prints data received from the image processor. In the print system, a first converter converts the input data to output data by processing the input data according to data type, while a detector detects a specified pattern in the converted data. All the converted data passes the detector, so that the specified pattern is detected surely or the detection of the image is not missed. Further, a second converter converts the converted data according to data type to data of output colors of an image output device, and the detector detects the specified pattern in the further converted data. Thus, an image having a color close to the original one can be detected surely.
    Type: Application
    Filed: June 15, 2001
    Publication date: May 22, 2003
    Inventors: Akira Murakawa, Kenji Masaki, Hirotomo Ishii
  • Patent number: 6487684
    Abstract: When the user performs input seeking a message that pertains to the status of the device, the message display device of the present invention selects and displays based on the data generated by a data generator comprising a counter and/or a sensor an appropriate message from a group of messages, each of which corresponds to various input contents.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: November 26, 2002
    Assignee: Minolta Co., Ltd.
    Inventor: Hirotomo Ishii
  • Publication number: 20020054315
    Abstract: In an image processor in a print system, an output device processes input data and outputs the processed data, while a detector detects whether data of a specified pattern is included in the input data or in the processed data, in parallel to the data processing by the output device. A stop controller makes the output device stop to output the processed data at an irregular timing after the detector detects the specified pattern. The printer prints an image on a sheet of paper, based on the data outputted by the output device. Thus when the specified pattern in an image is detected, the printing is stopped but the stop position becomes irregular.
    Type: Application
    Filed: June 15, 2001
    Publication date: May 9, 2002
    Inventors: Kenji Masaki, Hirotomo Ishii, Chiho Kawakami
  • Publication number: 20020047791
    Abstract: Considering that MOS transistors on a common integrated circuit can be controlled in resistance ratio between them with a relatively high accuracy, a DA converter is improved in accuracy by replacing resistors required to be accurate with MOS transistors without inviting an increase of the chip area. That is, between a high potential reference voltage (VrefH) and a low potential reference voltage (VrefL), a plurality of MOS transistors (M1-MN) are connected in series such that they normally operate in a linear region and at least one turns OFF during power-down periods of the DA converter. One of partial voltages (V1-VN) of these MOS transistors (M1-MN) is selected by switches (SW1-SWN) controlled in ON-OFF motion by a control signal obtained by decoding a digital input (12) in a decoder (11), and delivered to an analog output (13), such that an analog value corresponding to the digital data given from the digital input (12) is sent out from the analog output 13.
    Type: Application
    Filed: August 29, 2001
    Publication date: April 25, 2002
    Inventor: Hirotomo Ishii
  • Patent number: 6359510
    Abstract: A balanced type DDA 1 is combined with a single end type DDA 2 to form a differential amplifier circuit 3 which is a balanced type DDA. The balanced type DDA 1 has four input terminals VPP, VPN, VNN and VNP which are input terminals of two differential input stages, and two output terminals VoutP and VoutN which are output terminals of two output stages. These terminals are four input terminals and two output terminals of the differential amplifier circuit 3. The single end type DDA 2 has four input terminals, which are input terminals of two differential input stages and which are connected to the four input terminals of the differential amplifier circuit 3, respectively. The single end type DDA 2 also has an output terminal Vout of one output stage, which serves as a control output terminal for the feedback control of the differential amplifier circuit 3.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: March 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirotomo Ishii, Zdzislaw Czarnul
  • Publication number: 20020001095
    Abstract: In an image processor for detecting a circular pattern in an image, input image data is binarized to provide bi-level image data, and pixels having a predetermined value is counted in a block of a polygon having n vertices in the bi-level image data, wherein n denotes a natural number equal to or larger than eight. Then, it is decided, based on a number of the pixels having the predetermined value counted by the counter, whether the circular pattern is detected in the image or not. A detection window is used to detect the specified pattern. The detection window is moved successively by a predetermined number of pixels, in a direction from a side towards the center. The moving distance and direction are controlled based on the result of scan.
    Type: Application
    Filed: April 27, 2001
    Publication date: January 3, 2002
    Inventors: Chiho Kawakami, Akira Murakawa, Hirotomo Ishii
  • Publication number: 20010053250
    Abstract: An image processor detects a specified pattern defined by arrangement of three or more elements. Positions of a plurality of element candidates are detected based on input image data, and n pairs (n≧2) of element candidates are selected in the plurality of elements. Then, n arrangement criterions are determined based on the positions of the selected n pairs, and one arrangement criterion is determined based on the n arrangement criterions. By using the one arrangement criterion, positions of all the elements are calculated in the specified pattern. The specified pattern is detected based on the calculated positions of the arrangement.
    Type: Application
    Filed: May 4, 2001
    Publication date: December 20, 2001
    Inventors: Akira Murakawa, Hirotomo Ishii, Chiho Kawakami
  • Patent number: 6329849
    Abstract: The apparatus for converting a differential input voltage to two fully balanced output currents is achieved by providing a common mode control circuit of a simplified circuit construction to an operational transconductance amplifier. The apparatus includes an operational transconductance amplifier that is comprised of an OTA input section for converting two input voltages of the differential input voltage to a pair of interim output currents and an OTA output section for converting the interim output currents to the output currents, and a common mode controlling circuit for providing a control voltage to the OTA.
    Type: Grant
    Filed: November 12, 1999
    Date of Patent: December 11, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Zdzislaw Czarnul, Hirotomo Ishii, Kazuhiro Oda
  • Publication number: 20010035975
    Abstract: In order to carry out an image processing with high precision by using a simple structure, an image processing apparatus is provided with an input unit, a storage unit, a binarization unit, and a determination unit. The input unit inputs image data of an image. The storage unit stores a first condition on absolute positions of pixels in the image and a second condition on positions of pixels relative to a target pixel. The binarization unit binarizes the target pixel based upon a color data of the target pixel and that of at least one related pixel to the target pixel to generate a binarized value. The at least one related pixel in the image satisfies the first and second conditions. The determination unit determines whether or not the image has a specified pattern, based upon the binarized values.
    Type: Application
    Filed: May 1, 2001
    Publication date: November 1, 2001
    Inventor: Hirotomo Ishii
  • Patent number: 6246926
    Abstract: A sheet sorting apparatus capable of changing the discharge priority bin in accordance with the number of sheets. The sheet sorting apparatus discharges sheets from a specified discharge port into a corresponding bin. The bins are constructed so as to be readily removable, and the discharge priority bin is determined based on the estimated number of discharge sheets and the capacity of the bin.
    Type: Grant
    Filed: July 12, 1999
    Date of Patent: June 12, 2001
    Assignee: Minolta Co., Ltd.
    Inventors: Hirotomo Ishii, Atsushi Kondo