Abstract: The invention provides a standardized machining jig to be used in a machining center for processing various works. A machining jig 1 mounted on an exchange table T1 of a machining center has a jig base 10 and a pallet 20, and the pallet 20 is equipped with a large number of even-pitched through holes. Standard bolts 30 are inserted to the through holes, which are prevented from falling to the floor by a stopper plate 80. Standardized supporting blocks 42, 43 and positioning blocks 50 are fixed to the pallet 20 via bolts 30. A work 100 is fixed to the supporting blocks and the positioning blocks. The bolts 30 are manipulated via a bolt runner 60 attached to a robot arm.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

Abstract: A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

Abstract: A semiconductor memory includes a first decoder selecting any of modes 1-n of a test mode B according to first to fourth data signals, and a second decoder selecting any of modes 1-n of the test mode B according to fifth to eighth data signals. When a predetermined mode m+1 is not set in a test mode A, the mode selected by both the first and second decoders is set. When the predetermined mode m+1 is set, the mode selected by the first decoder is set. Therefore, the test mode B can be set at the manufacturer side by connecting only four data input/output terminals to the tester.

Abstract: A DRAM performs data writing if a column activation signal ZCOLRE is activated with changing of an internal address Add and then an internal write control signal WDRV is activated by generation of a write signal WE from an outside. However, in order to solve a problem that data writing does not performed in some cases when the data writing is performed at optional timing, a semiconductor memory device according to the present invention includes a delay unit, thereby delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated, even when the write signal WE is generated.

Abstract: When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

Abstract: In a semiconductor memory device, a refresh circuit outputs a refresh command signal for executing refresh operation. The refresh circuit includes a command-signal activating circuit for activating the refresh command signal, and a determination circuit for determining whether the activated refresh command signal is to be output. The determination circuit determines that the activated refresh command signal is to be output when the semiconductor memory device is in a standby state. Thereby, the semiconductor memory device enables stable refresh operation to be executed.

Abstract: Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

Abstract: A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.

Abstract: A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the address transition detection signal is applied, the internal row activation signal is deactivated in accordance with generation timings of delayed restore period signal indicating whether the internal array is in a selected state and of the address transition detection signal to permit the next row access. With such a configuration, the next operation is allowed to start after an internal state is surely restored to an initial state. When the next address transition detection signal is applied during a period of a restoration operation, a column recovery operation, or a refreshing operation, data access is correctly performed without causing data destruction.

Abstract: A DRAM performs data writing if a column activation signal ZCOLRE is activated with changing of an internal address Add and then an internal write control signal WDRV is activated by generation of a write signal WE from an outside. However, in order to solve a problem that data writing does not performed in some cases when the data writing is performed at optional timing, a semiconductor memory device according to the present invention includes a delay unit, thereby delaying an output of the internal write control signal WDRV until the column activation signal ZCOLRE is activated, even when the write signal WE is generated.

Abstract: A plurality of semiconductor chips are mounted in the same package, and a power supply is shared by the output circuits of the chips. In this case, even though the internal circuit power supplies of the chips are turned off, since an output circuit is in an ON state, a through current may flow from another chip. Therefore, a circuit for setting transistors constituting the output circuits of the chips in high-impedance states when the power supplies for the internal circuits of the respective semiconductor chips are turned off is added.

Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.

Abstract: Successive data read access with a final address specified is detected by a command mode detecting circuit to set a command mode entry status. In the command mode entry, a command of designating an internal state is made acceptable in accordance with a predetermined external signal. Consequently, a semiconductor memory device that enters a command mode, maintaining compatibility of pins and signal timings with a conventional static memory is provided.

Abstract: An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

Abstract: The primary object of the present invention is to provide a touch panel which has an excellent contact level between a undercoat layer and a substrate on which the undercoat layer is formed. The secondary object of the present invention to provide a touch panel which is lightweight and provided with a wide operating temperature and impact resistance. The primary object is achieved by providing a metal layer between a conductive-layer forming member and an undercoat layer, the metal layer being formed from a single metal element or an alloy of metal elements. The secondary object of the present invention is achieved by using an amorphous polyolefine base resin sheet for forming conductive-layer forming members of the touch and display substrates and using a material for forming a supporting member so that a difference between linear expansion coefficients of the supporting member and each of the conductive-layer forming members is kept within 1×10−5/° C.