Patents by Inventor Hiroyasu Tanaka

Hiroyasu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210341425
    Abstract: A measurement device includes a sensor that detects a particular substance, a storage unit that stores calibration data that indicate a relationship between a measurement value of the particular substance and an output of the sensor, and a calculation unit that calculates the measurement value of the particular substance from the calibration data based on the output of the sensor. The calculation unit produces a first waveform where a plurality of first outputs of the sensor are normalized, produces a plurality of second waveforms where a plurality of second outputs of the sensor that are included in the calibration data are normalized. The calculation unit calculates a measurement value of the particular substance based on the first waveform and the plurality of second waveforms.
    Type: Application
    Filed: October 30, 2019
    Publication date: November 4, 2021
    Inventor: Hiroyasu TANAKA
  • Publication number: 20210288073
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: June 1, 2021
    Publication date: September 16, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Publication number: 20210280149
    Abstract: A content acquisition interface acquires a content. An information acquisition interface acquires traveling condition information on a vehicle. A control interface causes a display interface to display the content when the traveling condition information acquired by the information acquisition interface indicates an automatic driving level equal to or higher than a threshold value or causes the display interface to display information on traveling-based restriction when the traveling condition information acquired by the information acquisition interface does not indicate an automatic driving level equal to or higher than the threshold value.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 9, 2021
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hideki TANAKA, Hiroyasu MENO, Tomohiro UKAI, Nobuyuki TANIGAWA, Toshiaki IKEMATSU
  • Patent number: 11069710
    Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 20, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyasu Tanaka, Tomoaki Shino
  • Patent number: 11063064
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: July 13, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
  • Publication number: 20210126011
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Applicant: Kioxia Corporation
    Inventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
  • Publication number: 20210126012
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Applicant: Kioxia Corporation
    Inventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
  • Patent number: 10976326
    Abstract: A sensor according to a first embodiment of the present invention includes a flow channel to permit passage of a specimen, a first detection part that is located in the flow channel and has a first ligand specifically bindable to a first material in the specimen, and a second detection part that is located downstream of the first detection part in the flow channel and has a second ligand specifically bindable to the first material and/or a second material in the specimen.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: April 13, 2021
    Assignee: KYOCERA CORPORATION
    Inventors: Hiroyasu Tanaka, Yasutaka Ohashi, Hiroshi Katta
  • Patent number: 10942191
    Abstract: There is provided a sensor and the like which can detect a first substance with high accuracy. A sensor for detecting whether an analyte contains a first substance, includes a base and a detection section including a second substance immobilized on a surface of the base. The second substance includes an amino acid, a bond which can be cleaved by a reaction with an enzyme, and a first compound which is bonded to the amino acid by the bond and includes a first group capable of bonding to other substances, and the analyte is configured to be introduced to the detection section by being contacted with a third substance which generates the enzyme by a reaction with the first substance.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: March 9, 2021
    Assignees: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION, KYOCERA CORPORATION
    Inventors: Hiroyasu Tanaka, Hideharu Kurioka, Shinsuke Sando
  • Patent number: 10916559
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: February 9, 2021
    Assignee: Kioxia Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20210028185
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya FURUKAWA, Tomoaki SHINO, Mitsuhiro NOGUCHI, Shinichi WATANABE, Yukio NISHIDA, Hiroyasu TANAKA
  • Patent number: 10840257
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
  • Publication number: 20200348290
    Abstract: A measurement method according to one embodiment, includes: preparing a detecting section on an upper surface of a measurement device with a reaction substance that can react specifically with a detection substance and a correction substance, wherein the detecting section measures signal values based on reactions of the reaction substance; supplying the detection substance onto the detecting section; supplying the correction substance onto the detecting section; measuring a first signal value of the signal values based on a specific reaction between the detection substance and the reaction substance; measuring a second signal value of the signal values based on a specific reaction between the correction substance and the reaction substance; and correcting the first signal value using the second signal value.
    Type: Application
    Filed: January 23, 2019
    Publication date: November 5, 2020
    Inventors: Hideharu KURIOKA, Hiroyasu TANAKA
  • Publication number: 20200335517
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Publication number: 20200273883
    Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroyasu TANAKA, Tomoaki SHINO
  • Patent number: 10741583
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
  • Publication number: 20200243560
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
    Type: Application
    Filed: April 15, 2020
    Publication date: July 30, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 10685976
    Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: June 16, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyasu Tanaka, Tomoaki Shino
  • Publication number: 20200182798
    Abstract: There are provided a detection sensor, a detection sensor kit, a sensor device, a method for producing a detection sensor and a detection method which enable measurement by a simple operation. A detection sensor includes a detecting element, a first member and a second member. The detecting element detects a detection object contained in a sample. The first member includes a first channel portion, and the first channel portion includes a first storage section which stores a reagent which is fed to the detecting element. The second member is movable relative to the first member and includes a second channel portion. In the detection sensor, the first member and the second member are joined with each other and form a joined channel in which the first channel portion and the second channel portion communicate with each other.
    Type: Application
    Filed: September 27, 2017
    Publication date: June 11, 2020
    Applicant: Kyocera Corporation
    Inventor: Hiroyasu TANAKA
  • Patent number: RE48191
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota