Patents by Inventor Hiroyasu Tanaka

Hiroyasu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12162352
    Abstract: A display controller converts a detection target region contained within a detection range of an obstruction sensor group and extending from a vehicle to the periphery thereof into a virtual marker image and causes a virtual image to be displayed by superimposing the image over a scene in front of the vehicle. When the relative position of an obstruction is within the detection target region, the display controller causes an arc-shaped ripple spreading in a direction based on the relative position of the obstruction to be displayed in a region, of the virtual marker image, located in a direction based on the relative position of the obstruction. The display controller converts the important information into a notification image and causes the notification image to be displayed in a display medium. The display controller changes the display format of at least one of the virtual marker image or the notification image.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: December 10, 2024
    Assignee: PANASONIC AUTOMOTIVE SYSTEMS CO., LTD.
    Inventors: Naoki Tanaka, Yasutoshi Yamamoto, Tomoka Ishibashi, Hiroyasu Makino
  • Publication number: 20240397721
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: August 7, 2024
    Publication date: November 28, 2024
    Applicant: Kioxia Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Publication number: 20240365549
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Application
    Filed: July 8, 2024
    Publication date: October 31, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
  • Patent number: 12129627
    Abstract: Provided is a work vehicle capable of satisfying a user's demand to brake performance in a flexible manner. A wheel loader 1 comprises a controller 5 storing a plurality of control characteristics each of which is set such that a brake valve control pressure Pi of a solenoid proportional valve 45 increases as a pedal angle ? of a brake pedal 43 increases, and under the condition where a pedal angle ? is equal to or less than a predetermined pedal angle ?, an increase rate of the brake valve control pressure Pi with respect to the pedal angle ? varies. In a case where the pedal angle ? detected by a potentiometer 33 is equal to or less than the predetermined pedal angle ?th, the controller 5, calculates the brake valve control pressure Pi based on the selected one control characteristic.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: October 29, 2024
    Assignee: HITACHI CONSTRUCTION MACHINERY CO., LTD.
    Inventors: Shinichiro Tanaka, Hiroyasu Kodera
  • Publication number: 20240355565
    Abstract: An electromagnetic relay includes a contact device, a movable member, a driving device, a return spring, and an insulating member. The contact device includes a first fixed terminal, a second fixed terminal, and a movable contact piece. The movable member presses the movable contact piece. The driving device is disposed on one side of a first direction with respect to the contact device and the movable member and moves the movable contact piece via the movable member to one side of a second direction intersecting the first direction. The return spring is disposed between the movable member and the driving device in the first direction for urging the movable member toward another side of the second direction. The insulating member separates the contact device from the driving device and has an opening where the return spring is inserted. The opening is open toward one side of the first direction.
    Type: Application
    Filed: April 5, 2024
    Publication date: October 24, 2024
    Inventors: Takeshi NISHIDA, Ayaka MIYAKE, Hiroyasu TANAKA
  • Publication number: 20240355564
    Abstract: An electromagnetic relay includes a contact device, a driving device, an insulating member, and a cover. The contact device includes a first fixed terminal, a second fixed terminal, and a movable contact piece. The driving device generates an electromagnetic force to move the movable contact piece. The insulating member is fixedly attached to the driving device and separates the contact device from the driving device. The cover is fixed to the insulating member and defines an accommodation space together with the insulating member to accommodate the contact device. One of the insulating member and the cover includes a plurality of convex portions projecting toward the other of the insulating member and the cover. The other of the insulating member and the cover includes a plurality of concave portions to be fixed to the plurality of convex portions.
    Type: Application
    Filed: April 5, 2024
    Publication date: October 24, 2024
    Inventors: Takeshi NISHIDA, Ayaka MIYAKE, Hiroyasu TANAKA
  • Patent number: 12089410
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Grant
    Filed: July 7, 2023
    Date of Patent: September 10, 2024
    Assignee: Kioxia Corporation
    Inventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
  • Patent number: 12058862
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: August 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Publication number: 20240138150
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: Kioxia Corporation
    Inventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO
  • Patent number: 11903205
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Patent number: 11903207
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: February 13, 2024
    Assignee: Kioxia Corporation
    Inventors: Masaru Kito, Hideaki Aochi, Ryota Katsumata, Akihiro Nitayama, Masaru Kidoh, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Yasuyuki Matsuoka, Mitsuru Sato
  • Publication number: 20240008276
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
    Type: Application
    Filed: September 12, 2023
    Publication date: January 4, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KIRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
  • Patent number: 11844218
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 12, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Patent number: 11815489
    Abstract: A measurement device includes a sensor that detects a particular substance, a storage unit that stores calibration data that indicate a relationship between a measurement value of the particular substance and an output of the sensor, and a calculation unit that calculates the measurement value of the particular substance from the calibration data based on the output of the sensor. The calculation unit produces a first waveform where a plurality of first outputs of the sensor are normalized, produces a plurality of second waveforms where a plurality of second outputs of the sensor that are included in the calibration data are normalized. The calculation unit calculates a measurement value of the particular substance based on the first waveform and the plurality of second waveforms.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 14, 2023
    Assignee: KYOCERA Corporation
    Inventor: Hiroyasu Tanaka
  • Publication number: 20230363167
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Application
    Filed: July 7, 2023
    Publication date: November 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Yoshiaki FUKUZUMI, Shinya ARAI, Masaki TSUJI, Hideaki AOCHI, Hiroyasu TANAKA
  • Patent number: 11792992
    Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: October 17, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
  • Patent number: 11744075
    Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: August 29, 2023
    Assignee: Kioxia Corporation
    Inventors: Yoshiaki Fukuzumi, Shinya Arai, Masaki Tsuji, Hideaki Aochi, Hiroyasu Tanaka
  • Publication number: 20230146470
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritahle memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of colunmar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 11, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
  • Patent number: 11574926
    Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
    Type: Grant
    Filed: October 12, 2021
    Date of Patent: February 7, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
  • Publication number: 20220328517
    Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
    Type: Application
    Filed: May 20, 2022
    Publication date: October 13, 2022
    Applicant: Kioxia Corporation
    Inventors: Masaru KITO, Hideaki AOCHI, Ryota KATSUMATA, Akihiro NITAYAMA, Masaru KIDOH, Hiroyasu TANAKA, Yoshiaki FUKUZUMI, Yasuyuki MATSUOKA, Mitsuru SATO