Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A control device for a continuously variable transmission with an auxiliary transmission includes: a cooperative control section being configured to shift the auxiliary transmission mechanism during the first inertia phase time period, and to shift the variator during the second inertia phase time period, when the cooperative control in which an input torque to the continuously variable transmission is equal to or smaller than a predetermined value in the cooperative control is judged, and being configured to shift the auxiliary transmission mechanism during the first inertia phase time period, and to shift the variator during the first inertia phase time period when the cooperative control in which the input torque to the continuously variable transmission is greater than the predetermined value is judged.

Abstract: In a vehicle on which a torque converter having a lock-up clutch is mounted between an engine and a transmission, a meet point learning controller is provided to perform learning control for obtaining a learning value based on information on a meet point at which the lock-up clutch starts torque transmission. The meet point learning controller estimates a LU transmission torque based on a difference between an engine torque signal value and a torque converter transmission torque when the lock-up clutch moves from a non-engaged state to an engaged state during traveling of the vehicle, and uses, as the meet point information, a meet point detection pressure at a time when the LU transmission torque estimated value is determined to have entered an upward trend.

Abstract: CVT controller has rotation speed sensors detecting driving and driven wheel rotation speed; driving and driven wheel speed difference detection unit detecting wheel speed difference ?vfr; and bad road judgment unit judging that road is bad road when ?vfr is first value ?vfr_br or greater. CVT controller further has first belt clamping force increase unit increasing belt clamping force in case where road is judged to be bad road, as compared with case where road is not judged to be bad road; vibration detection unit detecting vehicle speed vibration fvsp; and second belt clamping force increase unit increasing belt clamping force when ?vfr is second value ?vfr_psec or greater or when fvsp is third value fvsp_psec or greater in case where road is not judged to be bad road, as compared with case where ?vfr is less than ?vfr_psec and case where fvsp is less than fvsp_psec.

Abstract: A sensor is provided with a sensor element which outputs a signal in accordance with a detected object contained in a specimen positioned on a detection part in an element surface and with a package which accommodates the sensor element inside it and has a passage including a space positioned on the element surface. A lower surface of the passage has the element surface and a lower surface of an inflow passage extending toward the space, and a gap is positioned between the lower surface of the inflow passage and the element surface. The element surface is positioned above the lower surface of the inflow passage.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer covering the circuit, and a second insulating layer including a first portion and a second portion between the substrate and the first insulating layer. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The first insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the first insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the second insulating layer.

Abstract: A control device for an automatic transmission includes a continuously variable transmission mechanism, a torque converter, a target transmission ratio calculation unit, a feedback control unit, and a phase compensation unit. The torque converter has a lock-up clutch. The target transmission ratio calculation unit is configured to calculate a target transmission ratio based on a travelling state. The feedback control unit is configured to perform feedback control based on an actual value indicative of a state of the continuously variable transmission mechanism. The phase compensation unit is configured to perform phase lead compensation of the feedback control based on the travelling state. The phase compensation control unit is configured to halt the phase lead compensation when an unstable travelling state of a vehicle is detected. The phase compensation control unit is further configured to release the lock-up clutch when the phase lead compensation is halted.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: An automatic transmission control device implements a downshift by disengagement of a clutch that is engaged in a gear position before the downshift. It is determined whether an engine state is in a predetermined region in which a change of an engine torque per a change of an accelerator pedal opening is smaller than that in another region, and the engine torque is within a predetermined range, and an engine rotational speed is within a predetermined range. It is determined whether an operating state is in a predetermined state of accelerator operation in which the accelerator pedal opening is larger than a predetermined value, and an accelerator pedal opening change rate has an absolute value smaller than a predetermined value. The downshift is inhibited in response to determination that the engine state is in the predetermined region and the operating state is in the predetermined state of accelerator operation.

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: The present invention provides a surface acoustic wave sensor capable of suitably controlling the flow of a liquid sample onto IDT electrodes. A surface acoustic wave sensor has a piezoelectric substrate, a first IDT electrode and a second IDT electrode which are located on the upper surface of the piezoelectric substrate and are separated from each other while sandwiching a detection part on the piezoelectric substrate therebetween, and the cover which forms the space being on the first IDT electrode, second IDT electrode, and the detection part and straddling them. On the lower surface of the cover, the detection part-facing surface facing the detection part has a smaller contact angle to the liquid sample than that of a pair of electrode-facing surfaces facing the first IDT electrode and second IDT electrode.

Abstract: A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer including a first portion and a second portion between the substrate and a second insulating layer, and the second insulating layer covering the circuit. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The second insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the second insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the first insulating layer.

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract: A control device for a continuously variable transmission with an auxiliary transmission includes: a cooperative control section; and a depression shift control section, wherein when an actual transmission gear ratio of the variator at the judgment of the depression shift control is higher than a first transmission gear ratio set as a lowest value of a control of the transmission gear ratio, the depression shift control section configured to downshift the variator, and to set a target transmission gear ratio at the shift of the variator to a second transmission gear ratio which is a restriction value that is higher than the first transmission gear ratio.

Abstract: A liquid specimen sensor includes a pair of first IDT electrodes and a pair of second IDT electrodes, a pair of first input connection conductors connected to one of the pair of first IDT electrodes and extending to the outside of the flow path, a pair of first output connection conductors connected to the other of the pair of first IDT electrodes and extending to the outside of the flow path, a pair of second input connection conductors connected to one of the pair of second IDT electrodes and extending to the outside of the flow path, and a pair of second output connection conductors connected to the other of the pair of second IDT electrodes and extending to the outside of the flow path. The sum of the line lengths in the flow path of the pair of first input connection conductors and the pair of first output connection conductors and the sum of the line lengths in the flow path of the pair of second input connection conductors and the pair of second output connection conductors are equal.

Abstract: According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.

Abstract: A storage device includes a circuit on a substrate, electrode layers stacked on the circuit, a channel layer penetrating the electrode layers in a stacking direction, a plate-shaped first wire between the electrode layers and the circuit and electrically connected to the channel layer, a second wire at a level between the circuit and the first wire, a third wire between the circuit and the second wire, a contact plug penetrating the electrode layers and the first wire in the stacking direction and electrically connected to the second wire, and a columnar support body penetrating the electrode layers and the first wire in the stacking direction. The columnar support body has a lower end in contact with the second wire or the third wire. The first wire has a through-via-hole above the second wire, and the contact plug and the columnar support body are disposed inside the through-via-hole.