Abstract: An automatic transmission control device implements a downshift by disengagement of a clutch that is engaged in a gear position before the downshift. It is determined whether an engine state is in a predetermined region in which a change of an engine torque per a change of an accelerator pedal opening is smaller than that in another region, and the engine torque is within a predetermined range, and an engine rotational speed is within a predetermined range. It is determined whether an operating state is in a predetermined state of accelerator operation in which the accelerator pedal opening is larger than a predetermined value, and an accelerator pedal opening change rate has an absolute value smaller than a predetermined value. The downshift is inhibited in response to determination that the engine state is in the predetermined region and the operating state is in the predetermined state of accelerator operation.

Abstract: A sensor apparatus includes a first cover member; a detection element including an element substrate located on the first cover member, and a detection portion configured to detect an analyte, the detection portion being located on the element substrate; a terminal located on the first cover member and electrically connected to the detection element; an intermediate cover member located on the first cover member and having a space with the detection element; a filler member located in the space between the detection element and the intermediate cover member; a second cover member configured to cover at least a part of the detection element and joined to at least one of the first cover member and the intermediate cover member; an inlet into which the analyte flows; and a flow passage which is continuous with the inlet, and extends at least to the detection portion.

Abstract: There is provided a sensing method which can detect a detection target with good sensitivity. A detection target sensing method includes supplying a detection target to a base having a first substance immobilized on a surface thereof, the detection target being bindable to the first substance; supplying a second substance to the base after the detection target is supplied thereto, the second substance being bindable to the detection target; and supplying a metal particle to the base after the second substance is supplied thereto, the metal particle being bindable to the second substance.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: To provide a biosensor including a suctioning mechanism while using a detection element such as a surface acoustic wave device, included are: a first cover member 1 including an element-accommodating recess 5 on an upper face thereof; a detection element 3 including an element substrate 10, and at least one detection unit 13 located on the upper face of the element substrate 10 to perform detection of an analyte; and a second cover member 2 joined to the first cover member 1 and covering the detection element 3, and including an inflow port 14 from which the analyte flows in and a groove 15 extending from the inflow port 14 to at least above the detection unit.

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

Abstract: According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.

Abstract: An RNA aptamer is provided with a sequence of linkage order of UAUUAGGACCA.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; a charge storage layer; a first conductor; a second conductor; and a third conductor. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends along a stacking direction of the stacked body. The first conductor is provided in the stacked body. The first conductor is in contact with the substrate. The second conductor includes a different material from the first conductor. The second conductor is in contact with a first portion of the first conductor. The third conductor includes a same material as the second conductor. The third conductor is in contact with a second portion of the first conductor.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; a charge storage layer; a first conductor; a second conductor; and a third conductor. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The semiconductor body extends along a stacking direction of the stacked body. The first conductor is provided in the stacked body. The first conductor is in contact with the substrate. The second conductor includes a different material from the first conductor. The second conductor is in contact with a first portion of the first conductor. The third conductor includes a same material as the second conductor. The third conductor is in contact with a second portion of the first conductor.

Abstract: According to one embodiment, a semiconductor memory device includes a substrate, a first semiconductor region, a second semiconductor region, an insulating layer, a gate electrode film, a gate insulating film, a first film, a second film, a first contact plug, and a second contact plug. The second film and the first film are arranged in the first direction. The first contact plug extends in the first film along a second direction. The second direction crosses the first direction. The first contact plug electrically connects to the first semiconductor region. The second contact plug extends in the second film along the second direction. The second contact plug electrically connects to the second semiconductor region. At least a part of the gate electrode film dose not overlap the first film in the second direction and dose not overlap the second film in the second direction.

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.

Abstract: A transmission controller executes synchronization shift of shifting a variator in a direction opposite to a speed ratio change direction of a sub transmission mechanism when shifting a sub transmission mechanism. When a gear position of the sub transmission mechanism is at the second gear position and an output increase request of a power source is made, the transmission controller prohibits the synchronization shift and shifts only the sub transmission mechanism from a second gear position to a first gear position.

Abstract: A control unit comprises determining unit for determining whether or not a predetermined elapsed time condition is established after a shift has been performed to a specific gear position reached by engaging a specific frictional engagement element of a stepped transmission mechanism, and restricting unit for prohibiting the stepped transmission mechanism from performing a shift back to the specific gear position while allowing a continuously variable transmission mechanism to perform shifts so that an automatic transmission is controlled to a target speed ratio until the determining unit determines that the predetermined elapsed time condition is established.

Abstract: Provided are a novel alicyclic ester compound and a method for producing a compound of general formula (1) at a high yield from a compound of general formula (2) and a compound of general formula (3).

Abstract: A semiconductor memory device includes a connecting member including a semiconductor material, a first electrode film, a first insulating film, a stacked body and three or more semiconductor pillars. The stacked body includes second electrode films and second insulating films that alternately stacked. The semiconductor pillars are arrayed along two or more directions, extend in a stacking direction, pierce through the stacked body and the first insulating film, and are connected to the connecting member. The device includes a third insulating film provided between the semiconductor pillars and the stacked body and between the connecting member and the first electrode film. A charge storage layer is provided at least between one of the second electrode films and the third insulating film.