Abstract: A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

Abstract: A method and structure for increasing the threshold voltage of vertical semiconductor devices. The method comprises creating a deep trench in a substrate whose semiconductor material has an orientation plane perpendicular to the surface of the substrate. Then, vertical transistors are formed around and along the depth of the deep trench. Next, two shallow trench isolation are formed such that they sandwich the deep trench in an active region and the two shallow trench isolation regions abut the active region via planes perpendicular to the orientation plane. Then, the channel regions of the vertical transistors are exposed to the atmosphere in the deep trench and then chemically etched to planes parallel to the orientation plane. Then, a gate dielectric layer is formed on the wall of the deep trench. Finally, the deep trench is filled with poly-silicon to form the gate for the vertical transistors.

Abstract: A method is provided for making a trench capacitor by forming a trench in a substrate. The trench is then widened and a sacrificial collar is formed on sidewalls of the widened trench. The trench is then vertically deepened to extend below the sidewalls of the sacrificial collar. Subsequently, a capacitor is formed in the trench below the sacrificial collar. An integrated circuit includes a deep trench structure formed in a single-crystal region of a semiconductor substrate including an upper trench portion, the upper trench portion having an opening of rectangular shape. A lower trench portion is formed below the upper trench portion. The lower portion may be widened to have a bottle shape. Alternatively, the upper trench portion may be widened relative to the lower trench portion.

Abstract: A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising: 1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or 2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process; supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE proc

Abstract: A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

Abstract: A method for forming shallow trench isolation (STI) for semiconductor devices. A first hard mask is deposited over a semiconductor wafer, and a second hard mask is deposited over the first hard mask. The semiconductor wafer includes a first etching zone and at least a second etching zone disposed beneath the first etching zone. The etch process for the first etching zone and the etch process for the at least one second etching zone are selected such that smooth sidewall surface structures are formed within the semiconductor device. The etch processes for each subsequent etching zone may alternate between non-selective and selective etch processes to preserve at least the first hard mask material.

Abstract: A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

Abstract: The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispherical silicon grain (HSG) is deposited on a lower region of the trench. The HSG is then oxidized, along with that portion of the silicon substrate not covered by HSG, to form a roughened surface in the trench, thereby enhancing the trench capacitance. Oxidation of the HSG and the substrate occurs simultaneously with formation of the buried plate, and the formed oxide may be stripped along with the collar, thereby providing a simpler and more robust capacitance enhancement scheme.

Abstract: The present invention provides a temperature compensator for a torque sensor, including a pair of coils, which are connected to an AC power supply circuit via transistors and in which inductances change in opposite directions depending on torque, and a torque detecting means which obtains a voltage difference between a first voltage and a second voltage output via smoothing circuits based on changes in inductance of each pair of coils, and outputs as a torque detection voltage, the temperature compensator having a correcting voltage extracting means for extracting a voltage between terminals of a transistor in the AC power supply circuit as a temperature correcting voltage, and a correcting means for correcting the torque detection voltage based on a temperature correcting voltage Vs extracted by the correcting voltage extracting means.

Abstract: A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

Abstract: In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

Abstract: A dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical MOSFET formed in a silicon substrate above the trench capacitor, the vertical MOSFET having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical MOSFET, the adjacent vertical MOSFET having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.

Abstract: In the course of forming a trench capacitor or similar structure, the sidewalls of an aperture in a substrate are lined with a film stack containing a diffusion barrier; an upper portion of the outer layer is stripped, so that the upper and lower portions have different materials exposed; the lower portion of the film stack is stripped while the upper portion is protected by a hardmask layer; a diffusion step is performed in the lower portion while the upper portion is protected; and a selected material such as hemispherical grained silicon is deposited selectively on the lower portion while the exposed surface of the upper portion is a material on which the selected material forms poorly, so that the diffusing material penetrates and the selected material is formed only on the lower portion.

Abstract: A method for forming high-density self-aligned contacts and interconnect structures in a semiconductor device. A dielectric layer thick enough to contain both interconnect and contact structures is formed on a substrate. A patterned hardmask is formed on the dielectric layer to define both the interconnect and contact structures. The openings for interconnect features are first formed by partially etching the dielectric layer selective to the hardmask. A second mask (e.g., a resist) is used to define the contact openings, and the dielectric layer is etched through the second mask, also selective to the hardmask, to expose the diffusion regions to be contacted. The patterned hardmask is used to help define the contact openings. Conductive material is then deposited in the openings which results in contacts and interconnects that are self-aligned. By first forming the openings for both interconnect and contacts, savings in processing steps may be obtained.

Abstract: MOSFETS are formed by implanting at least a portion of a semiconductor substrate with a depart of a first type to form a first well region, annealing the first well region, implanting the annealed first well region with nitrogen; forming a gate insulator above at least a portion of the first well region; and providing a gate electrode above the gate oxide and providing source/drain regions in the substrate below the gate oxide about the gate electrode.

Abstract: A method to self-align a lithographic pattern to a workpiece, the method including the steps of obtaining a workpiece having a predetermined pattern of features; modifying at least some of the features so that when a photoresist material is applied to the pattern, there is a substantial difference in reflectivity between two adjacent features, at least one of which has been modified; applying a photoresist material; masklessly exposing the photoresist material; developing the photoresist material, the substantial difference in reflectivity of the two adjacent features causing the developed photoresist material to reveal one adjacent feature but not the other.

Abstract: A direct sensing circuit and method for reading data from a memory cell connected to a bitline, with open bitline sensing without using a reference bitline signal, onto a data line in a data read operation. Prior to the data read operation, both the bitline and the data line are precharged to precharge voltages and a sense node is precharged to ground. A pFET device has its gate coupled to a signal developed on the bitline from the memory cell to detect and amplify the signal level thereof, and has its source coupled to a voltage source and its drain coupled to a sense node, such that the signal developed on the bitline determines the degree of turn-on of the pFET device. An nFET device has its gate coupled to the sense node to detect and amplify the signal level thereof, and has its drain coupled to the data line.

Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.

Abstract: A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.

Abstract: A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.