Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.

Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

Abstract: A shallow trench isolation structure for a semiconductor device and the method for manufacturing the shallow trench isolation device within a semiconductor substrate. The shallow trench isolation structure is divot-free and includes un-annealed dielectric material as the trench fill material. The intersection of the structure and the semiconductor surface in which it is formed, is free of silicon nitride, but the isolation structure may include a silicon nitride liner which is within the trench and recessed below the semiconductor surface.

Abstract: A process and solution for selectively wet etching a titanium based perovskite material disposed on a silicon oxide or silicon nitride substrate is disclosed herein. The solution is composed of hydrogen peroxide, an acid and deionized water. The solution is heated to a temperature between 25 and 90 degrees Celsius. The titanium based perovskite material may be barium strontium titanate, barium titanate, strontium titanate or a lead titanate. The solution selectively etches the perovskite material while the substrate is only minimally etched, if at all. The process and solution allows for an etching rate up to thirty times greater than conventional etching rates for similar perovskite materials selective to various substrate, barrier and mask layers, including SiO2.

Abstract: A process for forming an ultra-shallow junction depth, doped region within a silicon substrate. The process includes forming a dielectric film on the substrate, then implanting an ionic dopant species into the structure. The profile of the implanted species includes a population implanted through the dielectric film and into the silicon substrate, and a peak concentration deliberately confined in the dielectric film in close proximity to the interface between the dielectric film and the silicon substrate. A high-energy, low-dosage implant process is used and produces a structure that is substantially free of dislocation loops and other defect clusters. An annealing process is used to drive the peak concentration closer to the interface, and some of the population of the originally implanted species from the dielectric film into the silicon substrate.

Abstract: A short channel insulated gate field effect transistor has within the semiconductor body that houses the transistor a buried layer of the same conductivity type as the body but of higher impurity concentration. The buried layer is below the channel region and essentially extends only the distance between the drain and source regions of the transistor. The process to form the device provides high concentration in the region under the gate to suppress lateral depletion region expansion, while keeping a gradual junction in the vertical direction.

Abstract: A trench is formed. A first TEOS film is deposited in the trench. Thereafter, the first TEOS film is etched back by a wet etching method up to a planarized surface of a substrate. In this way, seams and a void generated during the first TEOS film deposition step are exposed. This is attained by performing the etching under the conditions that an etching rate for the TEOS film of the upper portion of the trench is larger than that for the TEOS film of the bottom portion of the trench. Thereafter, a second TEOS film is deposited in the trench.

Abstract: There is disclosed the process of forming a gate conductor for a semiconductor device. The process begins with the step of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer being of a doped glass material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.

Abstract: A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:

Abstract: An integrated circuit (IC) conductor and the process of making the conductor. The conductor may be a monofilament conductor, a clad conductor or a coaxial conductor. A trench is formed in a dielectric layer. An outer material layer is deposited on the dielectric layer and in the trench, thick enough that the outer material layer merges together in a seam over the trench forming a void under the seam. The outer material layer is dielectric for the monofilament conductor, a cladding material for the clad conductor and conducting material for the coaxial conductor. The void is filled with a conductor for a monofilament or clad conductors. An inner dielectric liner layer is formed on the walls of the void and a core conductor is formed on the liner layer for the coaxial conductor.

Abstract: The improved methods and apparatus for cleaning semiconductor wafers and other planar substrates using megasonic cleaning are characterized by the use of monitoring of gas content (i) the liquid flowing to the megasonic cleaning environment, (ii) the liquid in the megasonic cleaning environment, and/or (iii) liquid leaving the megasonic cleaning environment. The methods use information obtained from directly monitoring of the gas content to control the supply of gas-containing liquid to the wafer-cleaning environment to achieve improved cleaning performance on the application of megasonic energy to the cleaning liquid. The gas content information may be used to control the supply of gas containing liquid in real time or may be used to pre-program the controller to achieve a desired gas content in the cleaning bath liquid.

Abstract: Improved megasonic cleaning is obtained by use of an apparatus containing a plurality of transducers arranged to transmit a progressive megasonic wave through a liquid containing a planar surface of an object. The progression of the wave is preferably such that particles are carried by the wave toward the toward the edge of the wafer. The processes and apparatus are especially useful for cleaning wafers in the course of manufacturing integrated circuit chips.

Abstract: A method for removal of post reactive ion etch sidewall polymer rails on a Al/Cu metal line of a semiconductor or microelectronic composite structure comprising:1) supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber in which said composite structure is supported to form a water soluble material of sidewall polymer rails left behind on the Al/Cu metal line from the RIE process; removing the water soluble material with deionized water; and removing photo-resist from said composite structure by either a water-only plasma process or a chemical down stream etching method; or2) forming a water-only plasma process to strip the photo-resist layer of a semiconductor or microelectronic composite structure previously subjected to a RIE process;supplying a mixture of an etching gas and an acid neutralizing gas into a vacuum chamber on which said structure is supported to form a water soluble material of saidwall polymer rails left behind on the Al/Cu metal line from the RIE process; a

Abstract: Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

Abstract: Formation of watermarks during semiconductor processing can be prevented by rinsing silicon wafers in an organic solvent prior to drying. Water droplets on the silicon wafer surface are taken up by the solvent and film is formed over the wafer surface. Following this rinse, the wafer may be subjected to standard IPA-based drying techniques.

Abstract: Apparatus and method are provided for improved washing and drying of semiconductor wafers utilizing an enhanced "Marangoni effect" flow of liquid off of the wafers for superior prevention of watermarks (water spots) on integrated circuits (ICs) on the wafers. The apparatus includes a housing 12 which may be hermetically sealed, an open-top wash tank 60 within a lower part of the housing, a moveable rack 16 for holding the wafers either in the tank for washing or in an upper part of the housing for drying, apparatus 34 for supplying chilled (near freezing) de-ionized water (DIW) to a lower part of the tank, the DIW flowing within the tank and overflowing the top thereof, a pump 20 for draining overflowing DIW from the housing, and apparatus 40 for supplying to the housing organic vapor such as isopropyl alcohol (IPA) in a dry gas such as nitrogen. During wafer drying operation of the apparatus the pressure within the housing is kept at about one Torr or less.

Abstract: An EEPROM of NOR-type architecture is formed at high integration density and allows selective programming without selective production of hot electron currents in storage transistor channels. common transistor channel conductors are formed as n-wells running parallel to bit lines having a width of minimum lithographic feature size and separated by shallow trench isolation structures. Connections from bit lines and the n-wells to respective transistors is formed by sub-lithographic metal plugs formed in a self-aligned manner to sidewalls of a layered structure including floating gates and a control gate/word line conductor. Thus a cell size only slightly greater than four times the minimum lithographic feature size can be produced. Provision of a transistor connecting a bit line and an associated n-well unconditionally prevents hot electron current concentration in the gate oxide to increase durability during both programming and flash erasure to either logical state.