Patents by Inventor Hiroyuki Ban
Hiroyuki Ban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6768183Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.Type: GrantFiled: April 19, 2002Date of Patent: July 27, 2004Assignee: Denso CorporationInventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
-
Publication number: 20040136212Abstract: In a voltage booster, a voltage detection circuit detects a battery voltage as an input voltage. If the input voltage is lower than a threshold level, an oscillation circuit outputs a gate signal having a relatively high frequency to increase the driving performance of a driving circuit. If the input voltage is higher than the threshold level, the frequency of the gate signal is lowered so as to prevent the driving performance of the driving circuit from rising to an excessively high value. As a result, a predetermined boosted voltage can be obtained regardless of variations in input voltage without using a filter for eliminating noise.Type: ApplicationFiled: November 20, 2003Publication date: July 15, 2004Inventors: Hirofumi Abe, Hirokazu Itakura, Hiroyuki Ban, Shoichi Okuda, Kingo Ota
-
Publication number: 20040021520Abstract: In an operational amplifier, a differential amplifying circuit is configured to amplify an input voltage inputted from the input terminal. An outputting transistor is connected to the output terminal. A driving transistor is connected to the differential amplifying circuit and the outputting transistor. The driving transistor turns on according to a control signal supplied from the differential amplifying circuit to the driving circuit. The driving transistor is also configured to drive the outputting transistor according to the control signal. A control signal reducing circuit, when a voltage is applied on the driving transistor through the outputting transistor, is configured to reduce the control signal within a range that the driving transistor is kept to on state. The voltage applied on the driving transistor exceeds a predetermined threshold voltage.Type: ApplicationFiled: August 4, 2003Publication date: February 5, 2004Inventors: Hiroshi Imai, Mitsuru Aoki, Hiroyuki Ban
-
Publication number: 20040008079Abstract: In a power supply circuit, a main transistor, which transmits power from an input terminal to an output terminal, is controlled so that a detected voltage from an input voltage is consistent with a reference voltage indicating a target voltage. An output current is detected and a limited value of the output current is set so that the limited value increases gradually when the output voltage rises up to the target voltage. The main transistor is controlled so that the output current keeps a value less than or equal to the limited value. This configuration is able to suppress an overshoot of the output voltage, thanks to a gradually raised control of the limited value. Additionally, to avoid the influence of a ringing component of the input voltage, a delay control circuit to give a delay to the start of rise of the output voltage can be provided.Type: ApplicationFiled: July 11, 2003Publication date: January 15, 2004Inventors: Nobuyoshi Osamura, Takaharu Hutamura, Hiroyuki Ban
-
Publication number: 20030218246Abstract: In a semiconductor device, a plurality of bump electrodes are formed for a source pad or a drain pad. The bump electrodes and the source or drain pad are connected with each other through wiring patterns. Thus, the following effect is produced unlike cases where one bump electrode is connected with one source pad or one drain pad through a wiring pattern: An amount of current that passes through each of the bump electrodes can be reduced, so that a breakdown of the bump electrodes is lessened.Type: ApplicationFiled: May 19, 2003Publication date: November 27, 2003Inventors: Hirofumi Abe, Hiroyuki Ban, Yoshinori Arashima, Hirokazu Itakura, Takao Kuroda, Noriyuki Iwamori, Satoshi Shiraki
-
Publication number: 20030214034Abstract: A semiconductor device includes a substrate, a plurality of bump electrodes disposed on the substrate, and a support area for supporting the substrate in case of carrying the substrate. The support area is disposed on a surface of the substrate, on which the bump electrode is disposed, and is disposed at a predetermined position, which is dotted on the surface of the substrate. In this device, the support area is sufficiently small, and the number of the bump electrodes can increase. Moreover, degree of freedom in a configuration of the support area increases.Type: ApplicationFiled: April 30, 2003Publication date: November 20, 2003Inventors: Hirofumi Abe, Hiroyuki Ban
-
Patent number: 6646319Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.Type: GrantFiled: June 20, 2002Date of Patent: November 11, 2003Assignee: Denso CorporationInventors: Hirokazu Itakura, Hiroyuki Ban
-
Patent number: 6605853Abstract: A semiconductor device has plural output circuits. Each of the plural output circuits has a semiconductor switching element and a heat protection circuit including a diode. When the heat protection circuit in a predetermined output circuit detects that heat emitted from the semiconductor switching element in the predetermined output circuit, the heat protection circuit turns off the semiconductor switching element in the predetermined output circuit. The plural output circuits are thermally isolated from each other by a trench and an insulation film. The trench and the insulation film prevent the heat from being transmitted from the predetermined output circuit to an adjacent output circuit. Therefore, even if the heat, by which the semiconductor switching element in the predetermined output circuit is turned off, is generated at the predetermined output circuit, the semiconductor switching element in the adjacent output circuit is not turned off by the heat.Type: GrantFiled: July 23, 2001Date of Patent: August 12, 2003Assignee: Denso CorporationInventors: Hiroshi Imai, Hirokazu Itakura, Hiroyuki Ban
-
Patent number: 6531855Abstract: A series circuit including a capacitor and a resistor for detecting variation of the output voltage of dc power supply is further provided. During startup, a charge current corresponding to the rising rate of the output voltage flows through the series circuit. This reduces the base current of the power transistor to suppress the rising rate to suppress overshoot and undershoot. A clamp circuit is provided to the differential amplifier for detecting the error voltage. This prevents the saturation in the differential amplifier or limit the voltage variation amplitude to accelerate the operation of the operational amplifier and suppress undershoot. A delay circuit for disabling to driving circuit for the power transistor for the initial interval may be further provided to suppress the initial rapid rise of the output voltage.Type: GrantFiled: June 28, 2001Date of Patent: March 11, 2003Assignee: Denso CorporationInventors: Takeshi Miki, Junichi Nagata, Hiroyuki Ban
-
Publication number: 20030001224Abstract: A semiconductor device includes an output power device, which generates an electrical noise, and an on-chip circuit, to which the noise is transmitted. The output power device is surrounded by two isolating regions. The area between the two isolating regions is electrically connected to a field ground area by a first wiring line. The field ground area is electrically connected to a point of contact, which has ground potential. The area between the outer isolating region of the two isolating regions and another isolating region around the on-chip circuit is also electrically connected to the field ground area by a second wiring line. The first and second wiring lines are separated from each other. The electrical noise is transmitted to the field ground area and released to the point of contact. Therefore, the noise is attenuated and the transmission of the noise to the on-chip circuit is suppressed.Type: ApplicationFiled: June 20, 2002Publication date: January 2, 2003Inventors: Hirokazu Itakura, Hiroyuki Ban
-
Publication number: 20020153592Abstract: An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.Type: ApplicationFiled: April 19, 2002Publication date: October 24, 2002Inventors: Shigeki Takahashi, Satoshi Shiraki, Hiroaki Himi, Hiroyuki Ban, Osamu Seya
-
Patent number: 6465996Abstract: A constant voltage circuit robust to the input voltage lowering is disclosed. The invention is applied to a constant voltage circuit fed with an input voltage through first and second power conductors for transferring the input voltage to a load as an output voltage through an output transistor. An inventive constant voltage circuit is provided with a substitute circuit, responsive to a detection of the lowing of the input voltage to a predetermined voltage, for providing a substitute output path that is connected in parallel with the output transistor. Doing this minimize the degree of lowering of the second voltage due to the lowering of said first voltage. The output transistor may be nay of NPN and PNP transistors and P-type and N-type MOS FETs.Type: GrantFiled: March 6, 2001Date of Patent: October 15, 2002Assignee: Denso CorporationInventors: Junichi Nagata, Kiyoshi Yamamoto, Hirokazu Itakura, Masahiro Kitagawa, Hiroyuki Ban, Hiroyuki Kawabata, Shinichi Maeda
-
Publication number: 20020030472Abstract: A series circuit including a capacitor and a resistor for detecting variation of the output voltage of dc power supply is further provided. During startup, a charge current corresponding to the rising rate of the output voltage flows through the series circuit. This reduces the base current of the power transistor to suppress the rising rate to suppress overshoot and undershoot. A clamp circuit is provided to the differential amplifier for detecting the error voltage. This prevents the saturation in the differential amplifier or limit the voltage variation amplitude to accelerate the operation of the operational amplifier and suppress undershoot. A delay circuit for disabling to driving circuit for the power transistor for the initial interval may be further provided to suppress the initial rapid rise of the output voltage.Type: ApplicationFiled: June 28, 2001Publication date: March 14, 2002Inventors: Takeshi Miki, Junichi Nagata, Hiroyuki Ban
-
Publication number: 20020017697Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: ApplicationFiled: September 5, 2001Publication date: February 14, 2002Applicant: Denso CorporationInventors: Yasuhiro Kitamura, Toshio Sakakibara, Kenji Kohno, Shoji Mizuno, Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
-
Publication number: 20020014639Abstract: A semiconductor device has plural output circuits. Each of the plural output circuits has a semiconductor switching element and a heat protection circuit including a diode. When the heat protection circuit in a predetermined output circuit detects that heat emitted from the semiconductor switching element in the predetermined output circuit, the heat protection circuit turns off the semiconductor switching element in the predetermined output circuit. The plural output circuits are thermally isolated from each other by a trench and an insulation film. The trench and the insulation film prevent the heat from being transmitted from the predetermined output circuit to an adjacent output circuit. Therefore, even if the heat, by which the semiconductor switching element in the predetermined output circuit is turned off, is generated at the predetermined output circuit, the semiconductor switching element in the adjacent output circuit is not turned off by the heat.Type: ApplicationFiled: July 23, 2001Publication date: February 7, 2002Inventors: Hiroshi Imai, Hirokazu Itakura, Hiroyuki Ban
-
Publication number: 20010030532Abstract: A constant voltage circuit robust to the input voltage lowering is disclosed. The invention is applied to a constant voltage circuit fed with an input voltage through first and second power conductors for transferring the input voltage to a load as an output voltage through an output transistor. An inventive constant voltage circuit is provided with a substitute circuit, responsive to a detection of the lowing of the input voltage to a predetermined voltage, for providing a substitute output path that is connected in parallel with the output transistor. Doing this minimize the degree of lowering of the second voltage due to the lowering of said first voltage. The output transistor may be nay of NPN and PNP transistors and P-type and N-type MOS FETs.Type: ApplicationFiled: March 6, 2001Publication date: October 18, 2001Inventors: Junichi Nagata, Kiyoshi Yamamoto, Hirokazu Itakura, Masahiro Kitagawa, Hiroyuki Ban, Hiroyuki Kawabata, Shinichi Maeda
-
Patent number: 6287933Abstract: A semiconductor device having a thin film resistor which comprises at least chromium, silicon and nitrogen, and formed on a substrate with having a special ratio of the chemical composition, the semiconductor device having a characteristic such that variations of the resistance value thereof due to temperature variations can be effectively suppressed.Type: GrantFiled: January 3, 1992Date of Patent: September 11, 2001Assignee: Nippondenso Co., Ltd.Inventors: Makio Iida, Shoji Miura, Kanemitsu Terada, Hiroyuki Ban, Kiyoshi Yamamoto, Katsuyoshi Oda, Yoshihiko Isobe
-
Patent number: 6242787Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.Type: GrantFiled: November 15, 1996Date of Patent: June 5, 2001Assignee: Denso CorporationInventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
-
Patent number: 6157246Abstract: The present invention is aimed at avoiding noise generation accompanying switching actions in booster circuits for a load such as an air-bag driving circuit. In an air-bag driving circuit, which is designed to actuate an igniting transistor 13 in response to output of a collision detecting signal from a collision detector 7 for detecting a collision condition of a vehicle so as to supply an igniting current to a squib 11 based on a voltage boosted by booster circuits 4 and 5, the boosting operation of the booster circuits 4 and 5 is inhibited while the collision detecting signal is absent and started when the collision detecting signal is output from the collision detector 7.Type: GrantFiled: July 2, 1998Date of Patent: December 5, 2000Assignee: Denso CorporationInventors: Mitsuhiro Saitou, Hiroyuki Ban
-
Patent number: 6104094Abstract: A pad for input/output signals is formed on a first conductive type insulated island region interposing an insulating film therebetween. The insulated island region is electrically insulated and isolated from other semiconductor regions in a semiconductor substrate. A fixed potential is provided to the insulated island region through an n.sup.+ -type layer and an electrode. As a result, it is possible to prevent noise superimposed on the input/output signals from interfering in the operation of the other semiconductor regions, and to prevent noise produced in the other semiconductor regions from being superimposed on the input/output signals.Type: GrantFiled: March 17, 1998Date of Patent: August 15, 2000Assignee: Denso CorporationInventors: Hiroyuki Ban, Fukuo Ishikawa