Patents by Inventor Hiroyuki Ban

Hiroyuki Ban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6104078
    Abstract: A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: August 15, 2000
    Assignee: DENSO Corporation
    Inventors: Makio Iida, Mitsuhiro Saitou, Akitaka Murata, Hiroyuki Ban, Tadashi Suzuki, Toshio Sakakibara, Takayuki Sugisaka, Shoji Miura
  • Patent number: 6104076
    Abstract: A semiconductor device including a reduced surface field strength type LDMOS transistor which can prevent the breakdown of elements at channel formation portions when a reverse voltage is applied to its drain. A P well and an N well are formed in an N-type substrate to produce a double-well structure, with a source electrode being set to be equal in electric potential to the N-type substrate. The drift region of the N well has a dopant concentration to satisfy the so-called RESURF condition, which can provide a high breakdown voltage a low ON resistance. When a reverse voltage is applied to a drain electrode, a parasitic bipolar transistor comprising the N well, the P well and the N-type substrate develops to form a current-carrying path toward a substrate, so that the element breakdown at the channel formation portions is avoidable at the application of the reverse voltage.
    Type: Grant
    Filed: November 15, 1996
    Date of Patent: August 15, 2000
    Assignee: Denso Corporation
    Inventors: Yoshiaki Nakayama, Hiroshi Maeda, Makio Iida, Hiroshi Fujimoto, Mitsuhiro Saitou, Hiroshi Imai, Hiroyuki Ban
  • Patent number: 6088207
    Abstract: An over-voltage protection apparatus includes a power feed line. A load has a given low impedance. A current supplying device operates for supplying a current to the load via the power feed line. A load drive device operates for controlling the supply of the current to the load by the current supplying device. An over-voltage detecting device operates for detecting an over-voltage at the power feed line. A discharge command device operates for, when the over-voltage at the power feed line is detected by the over-voltage detecting device, controlling the load drive device to enable a discharge current to flow from the power feed line into the load and thereby to remove the over-voltage from the power feed line through discharge. A current detecting device operates for detecting the discharge current.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: July 11, 2000
    Assignees: Anden Co., Ltd., Denso Corporation
    Inventors: Akira Sugiura, Fukuo Ishikawa, Hiroyuki Ban
  • Patent number: 6081040
    Abstract: An alignment mark for determining a position of a thin film resistor formed on a semiconductor chip. The alignment mark is disposed on a capacitor formation region of the semiconductor chip. Because aluminum wiring members of the semiconductor chip are not disposed adjacent to the alignment mark within the capacitor formation region, the alignment mark can be precisely recognized. As a result, the position of the thin film resistor can be also precisely determined.
    Type: Grant
    Filed: March 16, 1998
    Date of Patent: June 27, 2000
    Assignee: Denso Corporation
    Inventors: Shoichi Okuda, Mitsuhiro Saitou, Hiroyuki Ban
  • Patent number: 6075403
    Abstract: A charge pump circuit comprises a plurality of capacitors arranged to charge and discharge for generating a charged-up voltage. An oscillation circuit generates a clock signal to be applied to the plurality of capacitors to alternately charge and discharge these charge-up capacitors. A monitoring circuit detects electrical potentials on at least two of the charge-up capacitors and controls the clock signal. An oscillating condition of the oscillation circuit based on the electrical potentials on the at least two of the charge-up capacitors.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: June 13, 2000
    Assignee: Denso Corporation
    Inventors: Takeshi Ishikawa, Tomohisa Yamamoto, Hiroyuki Ban, Junichi Nagata, Junji Hayakawa
  • Patent number: 6069520
    Abstract: A current mirror circuit includes an input transistor and an output transistor. A first bipolar transistor has a collector terminal connected to a predetermined reference portion of a current supply path of a power source and an emitter terminal connected to a collector terminal of the output transistor for absorbing an electrical potential difference between the reference portion and the collector terminal of the output transistor. A second bipolar transistor has a base terminal connected to the emitter terminal of the first bipolar transistor and a collector terminal connected to a base terminal of the first bipolar transistor for fixing an electrical potential of the collector terminal of the output transistor to a base-emitter voltage of the second bipolar transistor.
    Type: Grant
    Filed: July 9, 1998
    Date of Patent: May 30, 2000
    Assignee: Denso Corporation
    Inventors: Tomohisa Yamamoto, Hiroyuki Ban
  • Patent number: 6034556
    Abstract: An operational amplifier charges a charge storage capacitor in response to an input signal supplied to a non-inverting input terminal. When a switching signal is low, NPN transistors disposed in an output open circuit are on. Therefore, output transistors disposed in a push-pull circuit are off and the output signal is cut off. Further, in this situation, the potential of a phase compensation capacitor is held because AC coupling of the phase compensation capacitor does not occur.
    Type: Grant
    Filed: February 5, 1998
    Date of Patent: March 7, 2000
    Assignee: Denso Corporation
    Inventors: Takahisa Koyasu, Mitsuhiro Saitou, Hiroyuki Ban
  • Patent number: 5999041
    Abstract: An output MOS transistor and a current-detecting MOS transistor are connected commonly at their drains and gates. A gate voltage is fed to the gates of these transistors via signal lines. When the voltage of an output terminal is increased in response to excessive load current, a current-mirror circuit consisting of first and second transistors pulls in current from the signal line to reduce the gate voltage. Thus, the output current of output MOS transistor is limited within a predetermined level. Furthermore, a diode, provided in the signal line, produces a voltage drop equivalent to the base-emitter voltage of first transistor. By the function of this diode, the gate-source voltage of output MOS transistor is equalized with the gate-source voltage of current-detecting MOS transistor. As a result, the same operating point can be set for the output transistor and the current-detecting transistor.
    Type: Grant
    Filed: May 16, 1997
    Date of Patent: December 7, 1999
    Assignee: Denso Corporation
    Inventors: Junichi Nagata, Junji Hayakawa, Hiroyuki Ban
  • Patent number: 5994744
    Abstract: An analog switching circuit comprises an insulated-gate field-effect transistor (Q20) having two n-type input-side and outpu-side semiconductor regions (201, 202) and a p-type semiconductor substrate region 203, for controlling conductiveness between an input terminal (IN) and an output terminal (OUT) based on a gate potential. A surge pulse detecting circuit (1020), responsive to an electric potential (Vi) of the input terminal (IN), produces a detection signal of a surge pulse equivalent to a forward bias of a PN junction formed between the semiconductor substrate region (203) and the input-side semiconductor region (201). A substrate potential setting circuit (1010) varies an electric potential of the semiconductor substrate region (203) in response to the electric potential (Vi) of the input terminal (IN) when aby detection signal is produced.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: November 30, 1999
    Assignee: Denso Corporation
    Inventors: Tetsuya Katayama, Takeshi Miki, Junji Hayakawa, Hiroyuki Ban
  • Patent number: 5977755
    Abstract: A constant-voltage power supply circuit includes a first output device provided in a first power feed line from a dc power supply to a first load. The first output device includes a first voltage control element for controlling an output voltage to the first load. A first control device operates for detecting the output voltage from the first output device to the first load, and controlling the first voltage control element to equalize the output voltage from the first output device with a first predetermined constant voltage. A second power feed line is connected to the first power feed line for feeding electric power to a second load. A second output device provided in the second power feed line includes a second voltage control element for controlling an output voltage to the second load.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 2, 1999
    Assignee: Denso Corporation
    Inventors: Takeshi Miki, Junji Hayakawa, Hiroyuki Ban
  • Patent number: 5977756
    Abstract: A first switching element opens or closes a power supply route of an inductive load in accordance with a first driving signal. A clamping element prevents a voltage ot the power supply route from exceeding a first clamp voltage when the power supply route is opened. A second switching element opens or closes the current flow route, provided in parallel with the power supply route, in response to a second driving signal. A rectifying means is responsive to the second switching element to change the clamp voltage to a second clamp voltage when the first switching element is turned off. The second switching element is constituted by a MOSFET. A charging element charges a capacitor of MOSFET.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: November 2, 1999
    Assignee: Denso Corporation
    Inventors: Junichi Nagata, Junji Hayakawa, Hiroyuki Ban
  • Patent number: 5918982
    Abstract: A temperature detecting circuit detects the rise of ambient temperature, using a forward voltage drop across a diode. The temperature detecting circuit comprises a temperature detecting diode whose cathode is grounded, a first constant current supply device connected with the anode of the temperature detecting diode, for supplying a constant current Ia to the temperature-detecting diode, a rectifying diode whose cathode is connected with the anode of the temperature detecting diode, a second constant current supply device connected with the anode of the rectifying diode, for supplying a constant current Ib to the temperature-detecting diode, a comparator, and a transistor. When the voltage at the anode of the temperature-detecting diode is lower than a reference voltage, the comparator produces a high-level signal indicative of overheating.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: July 6, 1999
    Assignee: Denso Corporation
    Inventors: Junichi Nagata, Junji Hayakawa, Hiroyuki Ban
  • Patent number: 5889722
    Abstract: An IC which integrates an EPROM is disposed on a circuit board. Also, a pad for supplying a writing voltage to the EPROM and a voltage supplying circuit, for supplying a power voltage to power terminals of the IC, which includes a first transistor and a second transistor, are disposed on the circuit board. When the pad is supplied with a high voltage for writing the data in the EPROM, the first transistor is on, the second transistor is off, and the voltage is supplied to the EPROM as the writing voltage. When data are read from the EPROM after the circuit board is packaged, because the pad is not supplied with any voltage, the first transistor is off, the second transistor is on, and a reading voltage is supplied to the EPROM via the outer terminal.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: March 30, 1999
    Assignee: Denso Corporation
    Inventors: Koji Numazaki, Takahisa Koyasu, Hiroyuki Ban
  • Patent number: 5883483
    Abstract: In an actuation circuit for a stepping motor, one switching element and its associated coil are connected at one connecting point, while the other switching element and its associated coil are connected at another connecting point. A pair of switching circuits and a pair of rectifying circuits are provided between two connecting points. When one of switching elements is changed from an ON condition to an OFF condition, the voltage difference between two connecting points allows the current to flow in a designated direction through the switching circuit and the rectifying circuit combined, thereby releasing the energy stored in the coils.
    Type: Grant
    Filed: November 6, 1996
    Date of Patent: March 16, 1999
    Assignee: Denso Corporation
    Inventors: Junichi Nagata, Junji Hayakawa, Hiroyuki Ban
  • Patent number: 5838526
    Abstract: In a load actuation circuit of an emitter-follower circuit arrangement, a surge detection circuit detects a power surge voltage superposed on a power voltage of a power line. A feed circuit supplies current to a control electrode of an output transistor (i.e. emitter-follower transistor) from the power line to turn on the output transistor forcibly when any power surge voltage is detected by the surge detection circuit. Thus, the power surge voltage is absorbed by the output transistor.
    Type: Grant
    Filed: May 7, 1997
    Date of Patent: November 17, 1998
    Assignees: Anden Co. Ltd, Denso Corporation
    Inventors: Fukuo Ishikawa, Akira Sugiura, Masahisa Makino, Hiroyuki Ban
  • Patent number: 5739546
    Abstract: A semiconductor wafer, having a relatively wide power supply line and ground line, and which can also prevent short-circuiting between these lines. Multiple integrated circuit formation regions, whereon integrated circuits have been formed, are disposed on a semiconductor wafer. A silicon oxide film is formed on a silicon substrate, and a ground line conductor is formed on the silicon oxide film. This ground line conductor is extended over scribe lines. A layer insulation film composed of silicon oxide film is deposited on the silicon oxide film with the ground line conductor interposed therebetween, and a power supply line conductor is formed on the layer insulation film to overlap the ground line conductor. The power supply line conductor is extended over scribe lines. In the integrated circuit formation regions, a power supply pad and the power supply line conductor are electrically connected. A ground pad and the ground line conductor are also electrically connected.
    Type: Grant
    Filed: June 18, 1996
    Date of Patent: April 14, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Mitsuhiro Saitou, Kouji Numazaki, Hiroyuki Ban
  • Patent number: 5719522
    Abstract: A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.
    Type: Grant
    Filed: March 12, 1997
    Date of Patent: February 17, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Mitsuhiro Saitou, Hajime Ito, Kiyoshi Yamamoto, Hiroyuki Ban
  • Patent number: 5661332
    Abstract: A diffused resistor capable of suppressing variation of characteristics caused by leakage of current occurring under high-temperature conditions. An N-type layer is epitaxially grown on a P-type substrate, and an N-type resistor island isolated by a P-type isolation region is formed. A P-type diffused resistor is formed in the island. An N-type region of high impurity concentration is disposed in close proximity to the high-potential end of the P-type diffused resistor. An electrode is brought into contact with not only the high-potential end but also the N-type high-impurity concentration region through the same contact hole. Thus, a parasitic transistor, which is formed from the P-type diffused resistor, the N-type resistor island and the P-type substrate (P-type isolation region), can be prevented from turning on with a minimal increase of the element area.
    Type: Grant
    Filed: January 26, 1995
    Date of Patent: August 26, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Katsumi Nakamura, Tomohisa Yamamoto, Hiroyuki Ban
  • Patent number: 5563486
    Abstract: A driving circuit of a pulse motor for use in a vehicle odometer is provided. The driving circuit includes a pulse source for providing drive pulses, in sequence, to a plurality of phase coils of the pulse motor, and a wave-shaper for shaping leading and trailing edges of each of the drive pulses so as to vary at a given rate in plural steps for noiseless smooth rotation of the pulse motor.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: October 8, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tomohisa Yamamoto, Junji Hayakawa, Hiroyuki Ban, Tukasa Miyake, Masami Kataoka
  • Patent number: 5550465
    Abstract: A pulse signal generated by a car speed sensor is converted to an analog voltage by a F-V converter, and two sawtooth signals are formed by two sawtooth current generators based on the analog voltage. The sawtooth currents are then converted into two triangular wave voltages by two I-V converters. Three-stage function generators change the slope of each of the triangular wave voltages step by step and form an approximated sine wave voltage and an approximated cosine wave voltage. A zero-cross compensating circuit is provided in each of the first stage function generators and adjust the triangular voltage to cross zero point.
    Type: Grant
    Filed: May 16, 1995
    Date of Patent: August 27, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Tomohisa Yamamoto, Junji Hayakawa, Hiroyuki Ban