Patents by Inventor Hiroyuki Maruyama

Hiroyuki Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7263314
    Abstract: An image printing apparatus includes a control unit which controls a rotational speed of an image carrier; a detecting unit which detects data of the rotational speed; a storage unit which stores the rotational speeds up to n past rotation cycle of said image carrier; and a determining unit which determines whether a rotational speed difference between a latest rotational speed in a current rotation cycle and a rotational speed in n past rotation cycle before the current rotation cycle at a predetermined interval, which includes the same rotational position in respective rotation cycles and its near position, is more than a predetermined reference value, wherein said control unit controls the rotational speed of said image carrier by using the data of rotational speeds at a predetermined interval including the same rotational position in one or n past rotation cycle before the current rotation cycle, and further said control unit controls a rotational speed in a subsequent rotation cycle next to the current r
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 28, 2007
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Tadayuki Ueda, Hiroyuki Maruyama, Toshihiro Motoi, Kenji Izumiya, Ryuji Okutomi, Satoshi Ogata
  • Publication number: 20070114631
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 24, 2007
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20070105369
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 10, 2007
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Patent number: 7208391
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: April 24, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Patent number: 7201016
    Abstract: A refrigerant supply apparatus for supplying a refrigerant to a cooling target. The apparatus includes a refrigerant supply channel through which pure water as the refrigerant is supplied to the cooling target, an impurity removing unit disposed in an impurity removing channel which is a channel different from the refrigerant supply channel, a sensor which measures a purity of the pure water, and a valve which stops supply of the pure water to the cooling target when the purity of the pure water does not satisfy a predetermined standard.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: April 10, 2007
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroyuki Maruyama
  • Patent number: 7176121
    Abstract: A semiconductor device and a manufacturing method thereof are provided for the improvement of the reliability of copper damascene wiring in which a film between wiring layers and a film between via layers are comprised of an SiOC film with low dielectric constant. A film between wiring layers, a film between wiring layers, and a film between via layers are respectively comprised of an SiOC film, and stopper insulating films and a cap insulating film are comprised of a laminated film of an SiCN film A and an SiC film B. By doing so, it becomes possible to reduce the leakage current of the film between wiring layers, the film between wiring layers, and the film between via layers, and also possible to improve the adhesion of the film between wiring layers, the film between wiring layers, and the film between via layers to the stopper insulating films and the cap insulating film.
    Type: Grant
    Filed: October 15, 2003
    Date of Patent: February 13, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazutoshi Ohmori, Tsuyoshi Tamaru, Naohumi Ohashi, Kiyohiko Sato, Hiroyuki Maruyama
  • Publication number: 20060248919
    Abstract: A refrigerant supply apparatus for supplying a refrigerant to a target. The apparatus includes a tank which stores pure water as the refrigerant, a refrigerant supply channel which supplies the pure water to the target, an impurity removing unit which removes impurities of the pure water in the refrigerant supply channel, and a valve which stops supply of the pure water to the target and circulates the pure water in the refrigerant supply channel.
    Type: Application
    Filed: July 7, 2006
    Publication date: November 9, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Hiroyuki Maruyama
  • Publication number: 20060209275
    Abstract: Disclosed is an exposure apparatus for exposing a substrate through a reticle, that includes a cooling device configured to cooling first water supplied from a facility by use of second water supplied fro the facility and having a temperature lower than the first water, and a supplying system for supplying water cooled by the cooling device, to a heat source inside the exposure apparatus. Also disclosed is an exposure apparatus for exposing a substrate through a reticle, that includes a chamber in which an exposure process is to be carried out, a circulation system configured to circulate a gas through the chamber, a supplying system configured to supply water, supplied from a facility, to a heat source inside the exposure apparatus, and a heat exchanger configured perform heat exchange between a gas discharged out of the chamber by the circulation system and the water to be supplied to the heat source by the supplying system.
    Type: Application
    Filed: March 13, 2006
    Publication date: September 21, 2006
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Chiharu Kido, Hiroyuki Maruyama
  • Publication number: 20060176465
    Abstract: An alignment apparatus includes driving means having a movable element and a stator, a measurement unit which measures a position of a moving member moved by the driving means using measurement light, and a discharging unit to discharge gas existing in an optical path of the measurement light. The discharging unit is provided to the stator.
    Type: Application
    Filed: February 3, 2006
    Publication date: August 10, 2006
    Inventor: Hiroyuki Maruyama
  • Publication number: 20060171741
    Abstract: An image printing apparatus includes a control unit which controls a rotational speed of an image carrier; a detecting unit which detects data of the rotational speed; a storage unit which stores the rotational speeds up to n past rotation cycle of said image carrier; and a determining unit which determines whether a rotational speed difference between a latest rotational speed in a current rotation cycle and a rotational speed in n past rotation cycle before the current rotation cycle at a predetermined interval, which includes the same rotational position in respective rotation cycles and its near position, is more than a predetermined reference value, wherein said control unit controls the rotational speed of said image carrier by using the data of rotational speeds at a predetermined interval including the same rotational position in one or n past rotation cycle before the current rotation cycle, and further said control unit controls a rotational speed in a subsequent rotation cycle next to the current r
    Type: Application
    Filed: September 27, 2005
    Publication date: August 3, 2006
    Inventors: Tadayuki Ueda, Hiroyuki Maruyama, Toshihiro Motoi, Kenji Izumiya, Ryuji Okutomi, Satoshi Ogata
  • Patent number: 7084063
    Abstract: The copper interconnect formed by the use of a damascene technique is improved in dielectric breakdown strength (reliability). During post-CMP cleaning, alkali cleaning, a deoxidizing process due to hydrogen annealing or the like, and acid cleaning are carried out in this order. After the post-CMP cleaning and before forming an insulation film for a cap film, hydrogen plasma and ammonia plasma processes are carried out on the semiconductor substrate. In this way, a copper-based buried interconnect is formed in an interlayer insulation film structured of an insulation material having a low dielectric constant.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: August 1, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Junji Noguchi, Shoji Asaka, Nobuhiro Konishi, Naohumi Ohashi, Hiroyuki Maruyama
  • Patent number: 7079172
    Abstract: The invention concerns an image-forming apparatus employing a clock-generating circuit, which generates dot clock pulses utilized for an image-writing section of the image-forming apparatus. The clock-generating circuit includes a digital-delay dot clock adjusting section to generate first dot clock pulses having a predetermined number of pulses within a predetermined time interval at a constant exposing range of the image-writing section, wherein each period of the first dot clock pulses is slightly increased or reduced by changing a selection for a plurality of delayed clock pulses, which are generated by delaying clock-pulses, outputted from a reference oscillator, in slightly different delay times; and a jitter suppressing section to suppress a jitter component included in the first dot clock pulses, wherein the jitter suppressing section divides the first dot clock pulses to generate second dot clock pulses, and then, multiplies the second dot clock pulses to generate the dot clock pulses.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: July 18, 2006
    Assignee: Konica Corporation
    Inventors: Kenji Izumiya, Hiroyuki Maruyama, Tadayuki Ueda, Ryuji Okutomi, Eiji Nishikawa, Satoshi Ogata, Shinobu Kishi
  • Patent number: 7074691
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Grant
    Filed: June 10, 2005
    Date of Patent: July 11, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems C O., Ltd.
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Patent number: 7060589
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Grant
    Filed: February 11, 2005
    Date of Patent: June 13, 2006
    Assignees: Hitachi, Ltd., Hitachi Ulsi Systems Co., Ltd.
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20060078312
    Abstract: A picture processing apparatus is disclosed which includes: an acquiring device which, apart from a first picture sequence picked up for reproduction purposes, acquires a second picture sequence picked up in synchronism with the first picture sequence, the second picture sequence being made up of pictures wider in angle than those constituting the first picture sequence; a calculating device operable to calculate degrees of similarity between scenes each made up of a predetermined number of consecutive pictures included in the second picture sequence; and a linking device which, after appropriating the degrees of similarity calculated by the calculating device for the degrees of similarity between the corresponding scenes in the first picture sequence, links together those of the corresponding scenes which have high degrees of similarity in the first picture sequence.
    Type: Application
    Filed: August 3, 2005
    Publication date: April 13, 2006
    Applicant: Sony Corporation
    Inventors: Makoto Murata, Machiko Segawa, Keigo Ihara, Nobuyuki Matsushita, Eiji Takahashi, Ryu Aoyama, Caoyi Lu, Hiroyuki Maruyama, Brian Clarkson
  • Publication number: 20060044402
    Abstract: A picture processing apparatus is disclosed which processes pictures showing subjects wearing devices each assigned identification information. The picture processing apparatus includes: an acquiring mechanism acquiring a first picture sequence formed by the pictures showing the subjects wearing the devices, and a time series of the identification information assigned to the devices; and a clustering mechanism which, based on how the time series acquired by the acquiring mechanism is linked according to the identification information, links together scenes constituting the first picture sequence, the scenes having been picked up at corresponding points in time.
    Type: Application
    Filed: August 11, 2005
    Publication date: March 2, 2006
    Applicant: Sony Corporation
    Inventors: Machiko Segawa, Keigo Ihara, Nobuyuki Matsushita, Makoto Murata, Eiji Takahashi, Ryu Aoyama, Caoyi Lu, Hiroyuki Maruyama
  • Publication number: 20060011368
    Abstract: A system and method of interfacing data between a first electronic device and a second electronic device is disclosed. In one embodiment, the first and second electronic devices are cell phones manufactured by different manufacturers. The first electronic device can be the source device, and the second electronic device can be the target device. A data transfer hub having universal connectors is coupled with at least one of a plurality of adapter cables. The first and second electronic devices are connected to the data transfer hub using at least one of the plurality of adapter cables. The data transfer hub is connected to the computer system, wherein the computer system is configured to receive and transmit data from the first electronic device and the second electronic device. The data is then transmitted from the first electronic device to the second electronic device.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 19, 2006
    Inventors: Hiroyuki Maruyama, John Spencer, Clas Siversten, Tohru Iwama
  • Patent number: 6977759
    Abstract: Optical image reading equipment is disclosed, whereby a background color of a document can be changed depending on a processing of the acquired image. The equipment is provided with an illuminating member (32) for illuminating a document, a reading portion (30) for reading reflected light of the document, and a backing member provided at least in the reading position of the document. The backing member is disposed on the opposite side to the reading portion across the document. The backing member is configured by a member which produces background color outside the document changeable by means of electric control. Thus an image suitable for a successive processing can be output.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: December 20, 2005
    Assignee: Fujitsu Limited
    Inventors: Toshimitsu Kumagai, Hiroyuki Maruyama
  • Publication number: 20050237603
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: June 10, 2005
    Publication date: October 27, 2005
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe
  • Publication number: 20050239257
    Abstract: A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film.
    Type: Application
    Filed: June 10, 2005
    Publication date: October 27, 2005
    Inventors: Hidenori Sato, Norio Suzuki, Akira Takamatsu, Hiroyuki Maruyama, Takeshi Saikawa, Katsuhiko Hotta, Hiroyuki Ichizoe