Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Abstract: A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.

Abstract: A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

Abstract: A method for etching a poly-granular metal-based film includes providing a flow of a background gas in a plasma etching chamber containing a semiconductor structure including the poly-granular metal-based film formed over a substrate with a mask patterned over the poly-granular metal-based film. The method also includes applying a source power to generate a background plasma from the background gas, and providing a flow of a modifying gas while maintaining the flow of the background gas to generate a modifying plasma that produces a surface modification region with a substantially uniform depth in the top surface of the poly-granular metal-based film exposed by the mask. The method further includes stopping the flow of the modifying gas while maintaining the flow of the background gas, and applying a biasing power to the substrate to remove the surface modification region.

Abstract: A resistive random access memory (RERAM) apparatus and method for forming the apparatus are provided. Oxygen content control in the RERAM is provided. To provide oxygen content control, a via to an electrode of the RERAM is formed utilizing an oxygen-free plasma etch step. In one embodiment, the dielectric within which the via is formed is silicon nitride (SiN). In exemplary embodiments, the plasma chemistry is a hydrofluorocarbon (CxHyFz)-based plasma chemistry or a fluorocarbon (CxFy)-based plasma chemistry. In one embodiment, the resistive layer of the RERAM is a metal oxide. In another embodiment, the oxygen concentrations in the electrode of the RERAM under the via and outside the via are the same after formation of the via.

Abstract: Provided are embodiments for a semiconductor device. The semiconductor device includes a bottom electrode, wherein the bottom electrode is formed on a metal interconnect electrode, and a dielectric layer on a surface of the bottom electrode. The semiconductor device also includes a top electrode formed on a surface of the dielectric layer, wherein at least one of the top electrode or the bottom electrode is a plasma treated top electrode or plasma treated bottom electrode. Also provided are embodiments for a method of fabricating a resistive switching device where at least one of the plurality of layers of the memory stack is processed with a charge particle treatment.

Abstract: Embodiments of the present invention are directed to forming a Resistive Random Access Memory (RRAM) device with a spacer for electrode isolation. In a non-limiting embodiment of the invention, a memory stack including a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode is formed. A portion of the memory stack is removed to expose a sidewall of the top electrode and a spacer is formed on the sidewall of the top electrode. The spacer is positioned to encapsulate the top electrode, physically preventing a short between the top electrode and the bottom electrode.

Abstract: A method is presented for facilitating oxygen vacancy generation in a resistive random access memory (RRAM) device. The method includes forming a RRAM stack having a first electrode and at least one sacrificial layer, encapsulating the RRAM stack with a dielectric layer, constructing a via resulting in removal of the at least one sacrificial layer of the RRAM stack, the via extending to a high-k dielectric layer of the RRAM stack, and forming a second electrode in the via such that the second electrode extends laterally into cavities defined by the removal of the at least one sacrificial layer.

Abstract: Cross bar array devices and methods of forming the same include first electrodes arranged adjacent to each other and extending in a first direction. Second electrodes are arranged transversely to the first electrodes. An electrolyte layer is disposed between the first electrodes and the second electrodes, the electrolyte layer comprising a nitridated dielectric material.

Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.

Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.

Abstract: A method for manufacturing a semiconductor memory device includes depositing a bottom metal line layer on a dielectric layer, and patterning the bottom metal line layer into a plurality of bottom metal lines spaced apart from each other. In the method, a plurality of switching element dielectric portions are formed on respective ones of the plurality of bottom metal lines, and a top metal line layer is deposited on the plurality of switching element dielectric portions. The method further includes patterning the top metal line layer into a plurality of top metal lines spaced apart from each other. The plurality of top metal lines are oriented perpendicular to the plurality of bottom metal lines.

Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.

Abstract: Embodiments of the invention are directed to a fabrication method that includes forming a dielectric region of a wafer, forming a bottom contact embedded within the dielectric region such that a top surface of the bottom contact is exposed, and forming a dummy resistive switching element over the top surface of the bottom electrode. Portions of the dummy resistive switching element are exposed to at least one oxide source. The dummy resistive switching element is replaced with a resistive switching element stack.

Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.

Abstract: A resistive random access memory (RRAM), including a first electrode, a base oxide being connected to the first electrode, and a multivalent oxide being connected to the base oxide layer. The multivalent oxide switches oxidative states.

Abstract: A method is presented for constructing conductive bridging random access memory (CBRAM) stacks. The method includes forming a plurality of conductive lines within an interlayer dielectric (ILD), forming a CBRAM stack including at least an electrolyte layer, a conductive layer, a metal cap layer, and a top electrode such that a top end of the CBRAM stack has a smaller critical dimension than a bottom end of the CBRAM stack, forming a low-k dielectric layer over the CBRAM stack, and exposing a top surface of the CBRAM stack during a via opening.

Abstract: A method for forming a semiconductor device comprises receiving a substrate with a silicon oxide layer formed over the substrate and a nano-wire based semiconductor device formed using template-assisted-selective epitaxy (TASE) over the silicon oxide layer. The semiconductor device serves as a seed layer to form at least one i) silicon nanowire which extends laterally in the semiconductor device and over the silicon oxide layer, ii) tunnel which extends laterally in the semiconductor device and over the silicon oxide layer, and iii) nuclei on the silicon oxide layer. A film is deposited over the semiconductor device and the silicon oxide layer. The film is removed over silicon oxide layer outside the semiconductor device. Next the nuclei on the silicon oxide layer are removed. Finally, the silicon oxide layer over the semiconductor device is removed.

Abstract: Embodiments of the present invention are directed to forming a Resistive Random Access Memory (RRAM) device with a spacer for electrode isolation. In a non-limiting embodiment of the invention, a memory stack including a top electrode, a bottom electrode, and a dielectric layer between the top electrode and the bottom electrode is formed. A portion of the memory stack is removed to expose a sidewall of the top electrode and a spacer is formed on the sidewall of the top electrode. The spacer is positioned to encapsulate the top electrode, physically preventing a short between the top electrode and the bottom electrode.

Abstract: Devices and/or methods that facilitate forming a resistive memory crossbar array with a multilayer hardmask are provided. In some embodiments, a resistive random access memory (RRAM) can comprise a multilayer hardmask comprising three layers, an interlayer oxide between a first layer of silicon nitride and a second layer of silicon nitride. In other embodiments, an RRAM can comprise a multilayer hardmask comprising two layers, a layer of an oxide on a layer of silicon nitride.