Patents by Inventor Hiroyuki Miyazoe

Hiroyuki Miyazoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Thin film interconnects with large grains
    Patent number: 10170361
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert L Bruce, Cyril Cabral, Jr., Gregory M Fritz, Eric A Joseph, Michael F Lofaro, Hiroyuki Miyazoe, Kenneth P Rodbell, Ghavam G Shahidi
  • Tapered metal nitride structure
    Patent number: 10147782
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: December 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes
    Patent number: 10141509
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: November 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Hybrid subtractive etch/metal fill process for fabricating interconnects
    Patent number: 10128185
    Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: November 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Gregory M. Fritz, Eric A. Joseph, Hiroyuki Miyazoe
  • Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes
    Patent number: 10096773
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • CROSSBAR RESISTIVE MEMORY ARRAY WITH HIGHLY CONDUCTIVE COPPER/COPPER ALLOY ELECTRODES AND SILVER/SILVER ALLOYS ELECTRODES
    Publication number: 20180287060
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Application
    Filed: September 20, 2017
    Publication date: October 4, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • CROSSBAR RESISTIVE MEMORY ARRAY WITH HIGHLY CONDUCTIVE COPPER/COPPER ALLOY ELECTRODES AND SILVER/SILVER ALLOYS ELECTRODES
    Publication number: 20180287059
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Application
    Filed: March 30, 2017
    Publication date: October 4, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • CROSSBAR RESISTIVE MEMORY ARRAY WITH HIGHLY CONDUCTIVE COPPER/COPPER ALLOY ELECTRODES AND SILVER/SILVER ALLOYS ELECTRODES
    Publication number: 20180287061
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Application
    Filed: January 26, 2018
    Publication date: October 4, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Patterned sidewall smoothing using a pre-smoothed inverted tone pattern
    Patent number: 10068991
    Abstract: Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kafai Lai, Hari V. Mallela, Hiroyuki Miyazoe, Reinaldo A. Vega, Rajasekhar Venigalla
  • PATTERNED SIDEWALL SMOOTHING USING A PRE-SMOOTHED INVERTED TONE PATTERN
    Publication number: 20180240892
    Abstract: Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
    Type: Application
    Filed: February 21, 2017
    Publication date: August 23, 2018
    Inventors: Kafai Lai, Hari V. Mallela, Hiroyuki Miyazoe, Reinaldo A. Vega, Rajasekhar Venigalla
  • PATTERNED SIDEWALL SMOOTHING USING A PRE-SMOOTHED INVERTED TONE PATTERN
    Publication number: 20180240894
    Abstract: Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
    Type: Application
    Filed: January 19, 2018
    Publication date: August 23, 2018
    Inventors: Kafai LAI, Hari V. MALLELA, Hiroyuki MIYAZOE, Reinaldo A. VEGA, Rajasekhar VENIGALLA
  • Selective dry etch for directed self assembly of block copolymers
    Patent number: 10043668
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 7, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian U. Engelmann, Ashish V. Jagtiani, Hiroyuki Miyazoe, Hsinyu Tsai
  • SELECTIVE DRY ETCH FOR DIRECTED SELF ASSEMBLY OF BLOCK COPOLYMERS
    Publication number: 20180211831
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Application
    Filed: December 12, 2017
    Publication date: July 26, 2018
    Inventors: SEBASTIAN U. ENGELMANN, ASHISH V. JAGTIANI, HIROYUKI MIYAZOE, HSINYU TSAI
  • INTERCONNECT STRUCTURE INCLUDING AIRGAPS AND SUBSTRACTIVELY ETCHED METAL LINES
    Publication number: 20180204759
    Abstract: Integrated circuits including at least two electrically conductive interconnect lines and methods of manufacturing generally include a surface of the integrated circuit. At least two electrically conductive interconnect lines are separated by a space of less than 90 nm and are formed on the surface. Each of the at least two interconnect lines includes a metal cap, a copper conductor having an average grain size greater than a line width of the interconnect. A liner layer is provided, wherein the liner layer and the metal cap encapsulate the copper conductor. A dielectric layer overlaying the at least two electrically conductive interconnect lines and extending along sidewalls thereof is provided, wherein the dielectric layer is configured to provide an airgap between the at least two interconnect lines at the spacing.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 19, 2018
    Inventors: ROBERT L. BRUCE, ALFRED GRILL, ERIC A. JOSEPH, TEDDIE P. MAGBITANG, HIROYUKI MIYAZOE, DEBORAH A. NEUMAYER
  • HIGH-RESISTANCE MEMORY DEVICES
    Publication number: 20180197917
    Abstract: Cross bar array devices and methods of forming the same include first electrodes arranged adjacent to each other and extending in a first direction. Second electrodes are arranged transversely to the first electrodes. An electrolyte layer is disposed between the first electrodes and the second electrodes, the electrolyte layer comprising a nitridated dielectric material.
    Type: Application
    Filed: January 12, 2017
    Publication date: July 12, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe, Vijay Narayanan
  • Scaled cross bar array with undercut electrode
    Patent number: 9997704
    Abstract: A cross bar array device includes first electrodes arranged adjacent to each other and extending in a first direction, the first electrodes including a main electrode layer and a scalable electrode layer. Second electrodes are arranged transversely to the first electrodes, the second electrodes including a main electrode layer and a scalable electrode layer. An electrolyte layer is disposed between the scalable electrode layers of the first electrodes and the second electrodes. A scalable electrode is formed from a scalable electrode layer and includes an undercut having a side laterally recessed from a width of a corresponding main electrode.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • MULTIVALENT OXIDE CAP FOR ANALOG SWITCHING RESISTIVE MEMORY
    Publication number: 20180138401
    Abstract: A memory includes a base oxide provided between a first electrode and a second electrode, and a multivalent oxide provided between the first electrode and the second electrode. The multivalent oxide switches between at least two oxidative states.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 17, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • MULTIVALENT OXIDE CAP FOR ANALOG SWITCHING RESISTIVE MEMORY
    Publication number: 20180123033
    Abstract: A resistive random access memory (RRAM), includes a base oxide, and a multivalent oxide provided on the base oxide. The multivalent oxide switches between at least two oxidative states.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • MULTIVALENT OXIDE CAP FOR ANALOG SWITCHING RESISTIVE MEMORY
    Publication number: 20180123034
    Abstract: A resistive random access memory (RRAM), including a first electrode, a base oxide being connected to the first electrode, and a multivalent oxide being connected to the base oxide layer. The multivalent oxide switches oxidative states.
    Type: Application
    Filed: December 22, 2017
    Publication date: May 3, 2018
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Selective dry etch for directed self assembly of block copolymers
    Patent number: 9941121
    Abstract: Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: April 10, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sebastian U. Engelmann, Ashish V. Jagtiani, Hiroyuki Miyazoe, Hsinyu Tsai