Patents by Inventor Hiroyuki Miyazoe

Hiroyuki Miyazoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RESISTIVE SWITCHING MEMORY WITH REPLACEMENT METAL ELECTRODE
    Publication number: 20200052207
    Abstract: A method is presented for facilitating oxygen vacancy generation in a resistive random access memory (RRAM) device. The method includes forming a RRAM stack having a first electrode and at least one sacrificial layer, encapsulating the RRAM stack with a dielectric layer, constructing a via resulting in removal of the at least one sacrificial layer of the RRAM stack, the via extending to a high-k dielectric layer of the RRAM stack, and forming a second electrode in the via such that the second electrode extends laterally into cavities defined by the removal of the at least one sacrificial layer.
    Type: Application
    Filed: August 8, 2018
    Publication date: February 13, 2020
    Inventors: Takashi Ando, Hiroyuki Miyazoe, Seyoung Kim, Vijay Narayanan
  • RESISTIVE MEMORY CROSSBAR ARRAY WITH TOP ELECTRODE INNER SPACERS
    Publication number: 20200028076
    Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.
    Type: Application
    Filed: May 2, 2019
    Publication date: January 23, 2020
    Inventors: Takashi Ando, Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen
  • VERTICAL ARRAY OF RESISTIVE SWITCHING DEVICES HAVING RESTRICTED FILAMENT REGIONS AND TUNABLE TOP ELECTRODE VOLUME
    Publication number: 20190378876
    Abstract: Embodiments of the invention are directed to a vertical resistive device. A non-limiting example of the vertical resistive device includes a horizontal plate having a conductive electrode region and a filament region. An opening extends through the filament region and is defined by sidewalls of the filament such that the filament region is positioned outside of the opening. A conductive pillar is positioned within the opening and is communicatively coupled to the filament region.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Inventors: Takashi Ando, Robert L. Bruce, Hiroyuki Miyazoe, John Rozen
  • Patterned sidewall smoothing using a pre-smoothed inverted tone pattern
    Patent number: 10381463
    Abstract: Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kafai Lai, Hari V. Mallela, Hiroyuki Miyazoe, Reinaldo A. Vega, Rajasekhar Venigalla
  • Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes
    Patent number: 10366323
    Abstract: Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Marwan H. Khater, Seyoung Kim, Hiroyuki Miyazoe
  • Resistive memory crossbar array with top electrode inner spacers
    Patent number: 10361367
    Abstract: A method is presented for protecting resistive random access memory (RRAM) stacks within a resistive memory crossbar array. The method includes forming conductive lines within an interlayer dielectric (ILD), forming a metal nitride layer over at least one conductive line, forming a bottom electrode, forming a RRAM stack over the metal nitride layer, the RRAM stack including a first top electrode and a second top electrode, undercutting the second top electrode to define recesses, and filling the recesses with inner spacers.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hiroyuki Miyazoe, Iqbal R. Saraf, Shyng-Tsong Chen
  • SIDEWALL IMAGE TRANSFER ON MAGNETIC TUNNEL JUNCTION STACK FOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY PATTERNING
    Publication number: 20190189914
    Abstract: A method of forming a semiconductor structure includes forming a first spacer material over two or more mandrels disposed over a magnetoresistive random-access memory (MRAM) stack. The method also includes performing a first sidewall image transfer of the two or more mandrels to form a first set of fins of the first spacer material over the MRAM stack, and performing a second sidewall image transfer to form a plurality of pillars of the first spacer material over the MRAM stack. The pillars of the first spacer material form top electrodes for a plurality of MRAM cells patterned from the MRAM stack.
    Type: Application
    Filed: December 14, 2017
    Publication date: June 20, 2019
    Inventors: Hiroyuki Miyazoe, Nathan P. Marchack, HsinYu Tsai, Eugene J. O'Sullivan, Karthik Yogendra
  • METHOD OF FORMING FIELD EFFECT TRANSISTOR (FET) CIRCUITS, AND FORMING INTEGRATED CIRCUIT (IC) CHIPS WITH THE FET CIRCUITS
    Publication number: 20190164773
    Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Applicant: International Business Machines Corporation
    Inventors: John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe, Jeffrey C. Shearer, Takefumi Suzuki
  • Method of forming field effect transistor (FET) circuits, and forming integrated circuit (IC) chips with the FET circuits
    Patent number: 10304692
    Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe, Jeffrey C. Shearer, Takefumi Suzuki
  • DIRECTED SELF-ASSEMBLY FOR COPPER PATTERNING
    Publication number: 20190157106
    Abstract: A process for forming patterned copper lines, a pattern of copper lines, and an electronic device having patterned copper lines and at least one CMOS circuit. The process includes assembling an etch stack, wherein the etch stack includes a resist and a copper substrate. The process also includes lithographically patterning the resist to produce a template, and forming a patterned block copolymer mask layer by directed self-assembly. Additionally, the process includes etching portions of the block copolymer mask layer to produce a patterned block copolymer mask layer, and transferring a pattern formed by the template and the patterned block copolymer mask layer to the copper substrate to form the patterned copper lines.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 23, 2019
    Inventors: Eric A. Joseph, Hiroyuki Miyazoe, Adam M. Pyzyna, HsinYu Tsai
  • ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL)
    Publication number: 20190148453
    Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
    Type: Application
    Filed: December 20, 2018
    Publication date: May 16, 2019
    Applicant: International Business Machines Corporation
    Inventors: Robert Bruce, Fabio Carta, Gloria WingYun Fraczak, Hiroyuki Miyazoe, Kumar R. Virwani
  • ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL)
    Publication number: 20190123101
    Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Applicant: International Business Machines Corporation
    Inventors: Robert Bruce, Fabio Carta, Gloria WingYun Fraczak, Hiroyuki Miyazoe, Kumar R. Virwani
  • ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL)
    Publication number: 20190123100
    Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Applicant: International Business Machines Corporation
    Inventors: ROBERT BRUCE, Fabio Carta, Gloria WingYun Fraczak, Hiroyuki Miyazoe, Kumar R. Virwani
  • ACCESS DEVICE AND PHASE CHANGE MEMORY COMBINATION STRUCTURE IN BACKEND OF LINE (BEOL)
    Publication number: 20190115392
    Abstract: A combined semiconductor device is fabricated by forming a first access structure from a mixed ionic electronic conduction (MIEC) material. A first side of a first memory structure is electrically coupled with a first side of the first access structure to form the combination device. A subtractive etching process is applied to the combination device such that a surface of the combination device that is substantially orthogonal to a plane of a substrate of the semiconductor device is within a defined tapering tolerance.
    Type: Application
    Filed: October 16, 2017
    Publication date: April 18, 2019
    Applicant: International Business Machines Corporation
    Inventors: ROBERT BRUCE, Fabio Carta, Gloria WingYun Fraczak, Hiroyuki Miyazoe, Kumar R. Virwani
  • CRYOGENIC PATTERNING OF MAGNETIC TUNNEL JUNCTIONS
    Publication number: 20190115528
    Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 18, 2019
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Hiroyuki Miyazoe
  • THIN FILM INTERCONNECTS WITH LARGE GRAINS
    Publication number: 20190096757
    Abstract: The present disclosure relates to integrated circuits and to methods of manufacturing interconnects of integrated circuits. For example, an integrated circuit includes a surface of the integrated circuit and an interconnect formed on the surface and comprising a metal. An average grain size of the metal of the interconnect is greater than or equal to at least half of a line width of the interconnect. In another example, a method for manufacturing an interconnect of an integrated circuit includes depositing a layer of a metal onto a surface of the integrated circuit, annealing the metal, patterning a first hard mask for placement over the metal and forming a line of the interconnect and a first via of the interconnect by performing a timed etch of the metal using the first hard mask.
    Type: Application
    Filed: November 27, 2018
    Publication date: March 28, 2019
    Inventors: Robert L. Bruce, Cyril Cabral, JR., Gregory M. Fritz, Eric A. Joseph, Michael F. Lofaro, Hiroyuki Miyazoe, Kenneth P. Rodbell, Ghavam Shahidi
  • Hybrid subtractive etch/metal fill process for fabricating interconnects
    Patent number: 10236252
    Abstract: In one example, a method for fabricating an integrated circuit includes patterning a layer of a first conductive metal, via a subtractive etch process, to form a plurality of lines for connecting semiconductor devices on the integrated circuit. A large feature area is formed outside of the plurality of conductive lines via a metal fill process using a second conductive metal.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Gregory M. Fritz, Eric A. Joseph, Hiroyuki Miyazoe
  • TAPERED METAL NITRIDE STRUCTURE
    Publication number: 20190067413
    Abstract: A tapered metal nitride structure having a gentle sloping (i.e., tapered) sidewall is provided that includes an oxygen rich metal nitride portion located between each metal nitride portion of a stack of metal nitride portions. The structure is formed by incorporating/introducing oxygen into an upper portion of a first metal nitride layer to form an oxygen rich metal nitride surface layer. A second nitride is then formed atop the oxygen rich metal nitride surface layer. The steps of oxygen incorporation/addition and nitride layer formation may be repeated any number of times. An etch mask is then provided and thereafter a sputter etch is performed to provide the tapered metal nitride structure. The tapered metal nitride structure may be used as an electrode in a semiconductor device.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Martin M. Frank, Hiroyuki Miyazoe, Vijay Narayanan
  • Articles including ultra low dielectric layers
    Patent number: 10217661
    Abstract: An article may include a structure including a patterned metal on a surface of a substrate, the patterned metal including metal features separated by gaps of an average dimension of less than about 1000 nm. A porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupies all gaps. An interface between the metal features and the porous low dielectric constant material may include less than about 0.1% by volume of voids.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert L. Bruce, Geraud J. Dubois, Gregory Fritz, Teddie P. Magbitang, Hiroyuki Miyazoe, Willi Volksen
  • Cryogenic patterning of magnetic tunnel junctions
    Patent number: 10170697
    Abstract: Methods for forming magnetic tunnel junctions and structures thereof include cryogenic etching the layers defining the magnetic tunnel junction without lateral diffusion of reactive species.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony J. Annunziata, Chandrasekharan Kothandaraman, Nathan P. Marchack, Hiroyuki Miyazoe