Patents by Inventor Hiroyuki Mizuno

Hiroyuki Mizuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8829968
    Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.
    Type: Grant
    Filed: September 8, 2009
    Date of Patent: September 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
  • Patent number: 8832607
    Abstract: According to one embodiment, a method for making a correction map of a dose amount of EUV light used when exposing with the EUV light, includes estimating an exposure result based on an initial correction map of the dose amount and flare of the EUV light, determining a goodness of the exposure result, and correcting the initial correction map in the case where the exposure result is unacceptable. And, the correcting of the initial correction map, the estimating of the exposure result, and the determining of the goodness are repeated until the exposure result is good.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: September 9, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Koike, Hiroyuki Mizuno, Yosuke Okamoto
  • Publication number: 20140201503
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
    Type: Application
    Filed: March 17, 2014
    Publication date: July 17, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Publication number: 20140167819
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: February 21, 2014
    Publication date: June 19, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Patent number: 8713293
    Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue said second instruction with said operand varied in an operand value range determined as a function of the varying bias value.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: April 29, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kenichi Tashiro, Hiroyuki Mizuno, Yuji Umemoto
  • Patent number: 8683414
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 8674419
    Abstract: The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: March 18, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nozomu Matsuzaki, Hiroyuki Mizuno, Masashi Horiguchi
  • Patent number: 8674745
    Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 18, 2014
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuo Tanaka, Hiroyuki Mizuno, Rie Nishiyama, Manabu Miyamoto
  • Patent number: 8605478
    Abstract: In a sense circuit for DRAM memory cell a switch is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. VDL is the maximum amplitude voltage of the bit line BL. A sense amplifier SA comprises a first circuit including a differential MOS pair having the gate connected to the bit line BL and a second circuit connected to the local bit line LBL for full amplitude amplification and for holding the data. When the bit line BL and local bit line LBL are capacitance-coupled via a capacitor, it is recommended to use a latch type sense amplifier SA connected to the local bit line LBL.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: December 10, 2013
    Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroyuki Mizuno, Takeshi Sakata, Nobuhiro Oodaira, Takao Watanabe, Yusuke Kanno
  • Publication number: 20130252176
    Abstract: According to one embodiment, a method for making a correction map of a dose amount of EUV light used when exposing with the EUV light, includes estimating an exposure result based on an initial correction map of the dose amount and flare of the EUV light, determining a goodness of the exposure result, and correcting the initial correction map in the case where the exposure result is unacceptable. And, the correcting of the initial correction map, the estimating of the exposure result, and the determining of the goodness are repeated until the exposure result is good.
    Type: Application
    Filed: August 30, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takashi KOIKE, Hiroyuki Mizuno, Yosuke Okamoto
  • Publication number: 20130228939
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Application
    Filed: April 18, 2013
    Publication date: September 5, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Yusuke KANNO, Hiroyuki MIZUNO, Yoshihiko YASU, Kenji HIROSE, Takahiro IRITA
  • Patent number: 8441095
    Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: May 14, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Publication number: 20130035847
    Abstract: Navigation systems, methods, and programs acquire evaluation information for evaluating the driving of a vehicle, evaluate the driver's driving operation for each evaluation interval having a predetermined travel distance based on the evaluation information, and display a past evaluation result and a current evaluation result at a position corresponding to each evaluation interval on a map in a mode that differs between the past evaluation result and the current evaluation result. When the vehicle arrives at an end point of the evaluation interval of the past travel from the same direction as during the past travel time, the systems, methods, and programs evaluate the driver's driving operation for a current evaluation interval along a travel track of the current travel and display the current evaluation result on the current evaluation interval at a position which corresponds to the current evaluation interval and at which the past evaluation result is displayed.
    Type: Application
    Filed: June 22, 2012
    Publication date: February 7, 2013
    Applicant: AISIN AW CO., LTD.
    Inventors: Junki YAMAKAWA, Hiroyuki MIZUNO
  • Publication number: 20130026956
    Abstract: An injection molding machine according to the invention includes a motor, a driver circuit that drives the motor; and a rectifying part that supplies electric power to the driver circuit. A regenerative line for regenerative electric power of the motor is connected to the rectifying part in parallel. A converting part and a harmonics component reducing part are provided in the regenerative line. The converting part converts direct electric power between the driver circuit and the rectifying part into alternating electric power which is input to the harmonics component reducing part.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Inventors: Atsushi KATO, Hiroshi MORITA, Hiroyuki MIZUNO, Noritaka OKADA
  • Publication number: 20130026961
    Abstract: An injection molding machine includes a motor; a driver circuit; a rectifying part; a capacitor provided between the driver circuit and the rectifying part; a bridge circuit that converts direct electric power between the driver circuit and the rectifying part into alternating electric power; a harmonics component reducing part connected to an alternating side of the bridge circuit; and a regenerative line connected to the rectifying part in parallel, wherein the bridge circuit and the harmonics component reducing part are provided in the regenerative line, and plural switching elements of the bridge circuit are turned on or off such that electric power of the motor is regenerated when a voltage of the capacitor is greater than or equal to a predetermined value, and all the switching elements are turned off when the voltage of the capacitor is less than the predetermined value.
    Type: Application
    Filed: July 24, 2012
    Publication date: January 31, 2013
    Applicant: Sumitomo Heavy Industries, Ltd.
    Inventors: Noritaka OKADA, Hiroshi MORITA, Hiroyuki MIZUNO, Atsushi KATO
  • Patent number: 8364988
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Publication number: 20130018538
    Abstract: Evaluation indication systems, methods, and programs are provided for a hybrid vehicle that is configured to travel in an HV mode with an internal combustion engine or in an EV mode without the internal combustion engine. The systems, methods, and programs display a current position of the hybrid vehicle on a map, acquire current evaluations of fuel consumption of the hybrid vehicle in current travel by unit sections, acquire previous evaluations of fuel consumption of the hybrid vehicle in previous travel by unit sections, and indicate current evaluation icons on the map, each of the icons being an EV icon or art HV icon. Each EV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the EV mode and each HV icon indicates that the hybrid vehicle has travelled within the corresponding unit section in the HV mode.
    Type: Application
    Filed: June 14, 2012
    Publication date: January 17, 2013
    Applicant: AISIN AW CO., LTD.
    Inventors: Naoki MIURA, Junichi NONOMURA, Junki YAMAKAWA, Hiroyuki MIZUNO
  • Publication number: 20130018573
    Abstract: Evaluation indication systems, methods, and programs display a current position of a vehicle and a map around the current position on a display unit, acquire current evaluations that indicate evaluations of fuel consumption in current travel of the vehicle by unit sections, and acquire previous evaluations that indicate evaluations of fuel consumption of the vehicle in a past prior to the current travel by unit sections. The systems, methods, and programs indicate the current evaluations and the previous evaluations together by unit sections on the map.
    Type: Application
    Filed: June 14, 2012
    Publication date: January 17, 2013
    Applicant: AISIN AW CO., LTD.
    Inventors: Naoki MIURA, Junichi NONOMURA, Junki YAMAKAWA, Hiroyuki MIZUNO
  • Publication number: 20120318409
    Abstract: A steel material for a solid stabilizer which has high bendability, high hardenability, and high quenching crack resistance, a solid stabilizer having high strength, and a manufacturing method of the solid stabilizer. The steel material for the solid stabilizer contains, in mass %, 0.24 to 0.40% of C, 0.15 to 0.40% of Si, 0.50 to 1.20% of Mn, 0.03% or less of P, 0.30% or less of Cr, 0.01 to 0.03% of Ti, and 0.0010 to 0.0030% of B. The steel material for the solid stabilizer satisfies a condition of formula (1) below. Hardness in a radial center portion of the steel material for the solid stabilizer after tempering is 400 HV or more, and a martensite ratio in the radial center portion after the tempering is 80% or more. 1.24<(2C+0.1Si+0.4Mn+0.4Cr)×{1+(1.5B?300B2)×240}<1.
    Type: Application
    Filed: March 4, 2011
    Publication date: December 20, 2012
    Applicant: CHUO HATSUJO KABUSHIKI KAISHA
    Inventors: Hiroyuki Mizuno, Atsushi Sugimoto, Ichie Nomura, Takanori Kuno, Takayuki Sakakibara
  • Patent number: 8320703
    Abstract: An image processing method executes image processing to correct a non-uniform perceived resolution caused by image distortion correction, thereby achieving a uniform perceived resolution over an entire displayed image. The image processing method includes the step of adjusting an aperture compensation signal using distortion correcting data to correct a non-uniform perceived resolution caused in an image through partial conversion of magnification ratio by image distortion correction, thereby achieving a uniform perceived resolution.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: November 27, 2012
    Assignee: Sony Corporation
    Inventor: Hiroyuki Mizuno