Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF-overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control-electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: This invention is intended to build a system with service cores integrated. A user terminal sends authentication information and area information to an image service providing server via a network. The image service providing server receives the authentication information and the area information from the user terminal, selects an authentication server of an area corresponding to the area information from among authentication servers of all areas, and sends the authentication information received from the user terminal to the selected authentication server via the network. The authentication server receives the authentication information of the user terminal from the image service providing server and executes the authentication of the user terminal on the basis of the received authentication information. The present invention is applicable to image service providing systems which provide image-based services.

Abstract: A nonvolatile semiconductor memory device with high reliability (free from troubles in storing data), a high charge injection efficiency, and enabling parallel operation in a VG cell array, includes channel forming regions, a charge storing film which consists of stacked dielectric films and is capable of storing a charge, two storage portions forming parts of the charge storing film and overlapping the channel forming regions, a single layer dielectric film between the storage portions and in contact with the channel forming region, a control gate electrode on the single layer dielectric film, and a memory gate electrode on the storage portions.

Abstract: A nonvolatile semiconductor memory device with high reliability (free from troubles in storing data), a high charge injection efficiency, and enabling parallel operation in a VG cell array, includes channel forming regions, a charge storing film which consists of stacked dielectric films and is capable of storing a charge, two storage portions forming parts of the charge storing film and overlapping the channel forming regions, a single layer dielectric film between the storage portions and in contact with the channel forming region, a control gate electrode on the single layer dielectric film, and a memory gate electrode on the storage portions.

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: In method of manufacturing a DRAM by using a laminate SOI technique, which makes it possible to form a thin semiconductor film of a uniform thickness, the method includes steps of forming a step portion on a major surface of a silicon substrate, forming an insulating film on the major surface of the silicon substrate, forming a capacitor which is connected to the step potion through a contact hole formed through the insulating film on the step portion, grinding the silicon substrate from the other major surface thereof after a support substrate is laminated onto the silicon substrate to remain the step portion, forming a thin silicon film on the insulating film by lateral epitaxial growth process based on the silicon of the remaining step portion serving as a seed for the lateral epitaxial growth, and forming a MOS transistor in the thin silicon film.

Abstract: A micromilling device includes a milling chamber, a sorter located in the milling chamber for sorting solid material, nozzles for injecting a stream of solid particles to be milled into the chamber in a predetermined path, and impact elements positioned in the path for impacting the stream of solid material.

Abstract: In a method of manufacturing a DRAM by using a laminate SOI technique, which makes it possible to form a thin semiconductor film of a uniform thickness, the method includes steps of forming a step portion on a major surface of a silicon substrate, forming an insulating film on the major surface of the silicon substrate, forming a capacitor which is connected to the step potion through a contact hole formed through the insulating film on the step portion, grinding the silicon substrate from the other major surface thereof after a support substrate is laminated onto the silicon substrate to remain the step portion, forming a thin silicon film on the insulating film by lateral epitaxial growth process based on the silicon of the remaining step portion serving as a seed for the lateral epitaxial growth, and forming a MOS transistor in the thin silicon film.

Abstract: A micromilling device includes a milling chamber, at least one nozzle for injecting a stream of solid particles to be milled into the chamber in a predetermined path, and impact elements positioned in the path for impacting the stream of solid particles.