Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.

Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.

Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: A memory system includes a nonvolatile memory a controller that controls the nonvolatile memory, and a backup power supply. In response to a detection that power from an external source to the memory system is interrupted, at which time power to the memory system starts to be supplied from the backup power supply, the controller transmits a first command to the nonvolatile memory to change a parameter for a write operation and then transmits a second command to the nonvolatile memory to carry out a write operation, such that the nonvolatile memory carries out the write operation using the changed parameter.

Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Abstract: According to one embodiment, a memory system includes a memory and a memory controller. The memory includes a first buffer and a memory cell array. The memory controller includes a second buffer for receiving first data from a host. The memory controller transfers the first data to the first buffer without accumulating a predetermined size of the first data in the second buffer. The memory controller creates second data in the first buffer and programs the second data created in the first buffer into the memory cell array. The second data is formed of a plurality of third data. The third data is first data received from the memory controller by the memory. The size of the second data is equal to a size of a unit in which to program into the memory cell array.

Abstract: According to one embodiment, a semiconductor memory device includes a generator to generate an error correction code. The generator includes a first encoder to calculate a first error correction code, a second encoder to calculate a second correction code, and an operation part to operate the first error correction code and the second error correction code.

Abstract: According to one embodiment, a data storage apparatus includes an interface module and a controller. The interface module is configured to control rewritable nonvolatile memories provided for the respective channels. The controller is configured to write calibration data to the nonvolatile memories of any channel designated, through the interface module at the same time, in order to perform calibration.

Abstract: A storage device includes a memory having one or more storage regions each of which is assigned a physical address, and a controller having a writing control circuit configured to write data that is divided into a plurality of data units into logical storage positions, at least one of which is associated with two storage regions of the memory, and a conversion unit configured to perform a conversion process on a logical address of the logical storage position that is associated with two storage regions of the memory to generate physical addresses corresponding to the two storage regions of the memory.

Abstract: According to one embodiment, a data storage device includes a read module, an ECC module, and a controller. The read module is configured to read data to be accessed and designation data designating the data, from nonvolatile memories. The ECC module is configured to perform an error check and correction process on the data and designation data read by the read module. The controller is configured to correct the designation data if the ECC module cannot correct the designation data and to perform an error detection process based on the designation data corrected.

Abstract: According to one embodiment, a semiconductor memory device includes a command processing module, a plurality of storage units, a plurality of control modules, an adjustment circuit, and a setting register. The adjustment circuit is configured to exclude the control module connected to the storage unit of a second group from a write operation in accordance with identification data, and to cause the control module connected to the storage unit of the second group to perform a read operation in a period overlapping the write operation performed by the control module connected to the storage unit of a first group.

Abstract: According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Abstract: According to one embodiment, a data storage apparatus includes a memory module and a controller. The memory module has a plurality of flash memory chips. Data is written to or read from each flash memory chip having a specific page size as access unit. The controller is configured to supply memory control signals, which are independent of the common signal containing the data and addresses, to the flash memory chips, respectively, in order to write data larger than the specific data size to the memory module. In the memory module, the respective flash memory chips store the data, each at the same address, in response to the memory control signals.

Abstract: According to one embodiment, a data storage device includes a read module, an ECC module, and a controller. The read module is configured to read data to be accessed and designation data designating the data, from nonvolatile memories. The ECC module is configured to perform an error check and correction process on the data and designation data read by the read module. The controller is configured to correct the designation data if the ECC module cannot correct the designation data and to perform an error detection process based on the designation data corrected.

Abstract: According to one embodiment, a semiconductor storage device includes a queuing buffer, a read module, a separating module, a write command issuing module, and a write module. The write command issuing module is configured to add a write address indicated by write pointer information to the management data obtained by the separating module in order to issue a write command, and to automatically queue the write command into the queuing buffer. The write module is configured to supply the write command issued by the write command issuing module to the nonvolatile memory in order to write data into the nonvolatile memory.

Abstract: According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.