Patents by Inventor Hiroyuki Moro
Hiroyuki Moro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070181700Abstract: A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.Type: ApplicationFiled: April 12, 2007Publication date: August 9, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Moro
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Publication number: 20070030777Abstract: An optical disk device which decodes data recorded on an optical disk, comprises a first measuring unit which measure a cycle of a plurality of first synchronous signal regions VFO contained in a reproduction signal from an optical pickup, a cycle comparing unit which compares the measurement result of the first measuring unit with a first predetermined cycle, a second measuring unit which measures a cycle of a plurality of second synchronous signal regions SYNC which are contained in the reproduction signal from the optical pickup and have the cycle shorter than that of the plurality of first synchronous signal regions VFO, a cycle comparing unit which compares the measurement result of the second measuring unit with a second predetermined cycle, and an oscillator which generates a clock signal CKS for sampling the reproduction signal on the basis of the comparison results of the first and second cycle comparing units.Type: ApplicationFiled: August 3, 2006Publication date: February 8, 2007Inventors: Hideyuki Yamakawa, Koichi Otake, Yukiyasu Tatsuzawa, Hiroyuki Moro, Toshihiko Kaneshige, Hiroaki Morino
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Patent number: 7159075Abstract: A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.Type: GrantFiled: August 26, 2003Date of Patent: January 2, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Moro
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Publication number: 20060097061Abstract: A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.Type: ApplicationFiled: December 22, 2005Publication date: May 11, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Moro
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Publication number: 20060092824Abstract: According to this invention, an information recording medium has the first and second sides. The information recording medium includes the first information recording layer which includes the first reflecting layer reflecting incident light with a predetermined intensity from the first side, the second information recording layer which includes a second reflecting layer reflecting incident light with a predetermined intensity from the second side, an adhesion layer which adheres the first information recording layer and the second information recording layer, and a unique information recording area which is formed by burst-cutting the first reflecting layer and the second reflecting layer in correspondence with medium unique information, using incident light with an intensity higher than the predetermined intensity from one of the first side and the second side.Type: ApplicationFiled: October 17, 2005Publication date: May 4, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideyuki Yamakawa, Koichi Otake, Yukiyasu Tatsuzawa, Hiroyuki Moro, Nobuhisa Yoshida, Toshihiko Kaneshige
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Publication number: 20060092803Abstract: A pre-learning section pre-learns whether or not a signal characteristic has been changed by use of at least data in a plurality of data areas, and obtains an optimum equalization coefficient of an adaptive equalizer for the data areas after the signal characteristic has been changed, and then stores the optimum equalization coefficient in a optimum equalization coefficient storage section. On the basis of detection information from a reference information (VFO) area detection section, the optimum equalization coefficient pre-learned in a reference information (VFO) area is preset in the adaptive equalizer, and equalization coefficient learning processing for the adaptive equalizer is started after entering a next data area.Type: ApplicationFiled: October 28, 2005Publication date: May 4, 2006Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu Tatsuzawa, Hideyuki Yamakawa, Koichi Otake, Hiroyuki Moro, Toshihiko Kaneshige
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Publication number: 20060092804Abstract: A signal processing circuit on a stage previous to a maximum likelihood decoder is more stably automatically controlled to have an optimum characteristic. A pre-equalizer, an offset control unit, an asymmetry control unit, an amplitude control unit, an analog digital converter, an adaptive equalizer, and a maximum likelihood decoder are sequentially arranged. A frequency control device and a phase control device are arranged. A sequencer feeds back error information obtained by the maximum likelihood decoder to any two of the offset control unit, the asymmetry control unit, the amplitude control unit, the analog digital converter, and the adaptive equalizer when at least the frequency control and phase control are set in predetermined control ranges, respectively.Type: ApplicationFiled: October 28, 2005Publication date: May 4, 2006Inventors: Koichi Otake, Hideyuki Yamakawa, Yukiyasu Tatsuzawa, Hiroyuki Moro, Toshihiko Kaneshige
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Publication number: 20060023604Abstract: There is provided an apparatus which can flexibly cope with both of a signal reproduction process for a region with high recording density and a signal reproduction process for a region with low recording density. The apparatus includes a waveform equalizing circuit which subjects data read out from an optical disk to a waveform equalizing process, a plurality of PRML processors of different classes supplied with an output signal of the waveform equalizing circuit, a switch which selects one of output signals of the plurality of PRML processors and supplies the selected output signal to a decoder, and a controller which controls the switch according to high-density and low-density regions with different recording densities of the optical disk to set a selection state in which a corresponding one of the output signals of the plurality of PRML processors is selected.Type: ApplicationFiled: July 27, 2005Publication date: February 2, 2006Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideyuki Yamakawa, Koichi Otake, Yukiyasu Tatsuzawa, Hiroyuki Moro, Toshihiko Kaneshige
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Patent number: 6975252Abstract: A disk apparatus has a reading unit which reads reflection light from a disk and outputting a read signal, an identifying unit which identifies whether the read signal has been modified in accordance with a first modulation rule or has been modulated in accordance with a second modulation rule and outputs an identification signal, an equalizing unit which applies a waveform equalizing process to the read signal, and a decoding unit which carries out likelihood decoding of the waveform equalized read signal according to the modulation rule indicated by the identification signal from the identifying unit, and outputs a reproduction signal.Type: GrantFiled: December 21, 2004Date of Patent: December 13, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Yamakawa, Koichi Otake, Yukiyasu Tatsuzawa, Hiroyuki Moro, Toshihiko Kaneshige
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Publication number: 20050185559Abstract: A digital RF signal resulting from A/D conversion of an RF signal reproduced from an optical disk is compared with a plurality of set values, so that a predetermined waveform is detected from the digital RF signal. The wavelength of the detected waveform is measured, and the A/D conversion is controlled based on this wavelength. Comparing the digital RF signal with the plural set values enables high-accuracy waveform detection.Type: ApplicationFiled: February 1, 2005Publication date: August 25, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroyuki Moro, Toshihiko Kaneshige, Hideyuki Yamakawa, Koichi Otake, Yukiyasu Tatsuzawa
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Publication number: 20050141385Abstract: A disk apparatus has a reading unit which reads reflection light from a disk and outputting a read signal, an identifying unit which identifies whether the read signal has been modified in accordance with a first modulation rule or has been modulated in accordance with a second modulation rule and outputs an identification signal, an equalizing unit which applies a waveform equalizing process to the read signal, and a decoding unit which carries out likelihood decoding of the waveform equalized read signal according to the modulation rule indicated by the identification signal from the identifying unit, and outputs a reproduction signal.Type: ApplicationFiled: December 21, 2004Publication date: June 30, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hideyuki Yamakawa, Koichi Otake, Yukiyasu Tatsuzawa, Hiroyuki Moro, Toshihiko Kaneshige
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Publication number: 20050141373Abstract: A recorded stream generator generates a data block stream in synchronism with the phase of a recording clock, from the input data. The recorded stream generator further generates, for each predetermined data unit constituting the data block stream, a data phase reference pulse indicative of the phase of the data unit. An inserting section inserts a VFO signal into a predetermined amount (32 sectors) of the data block stream, the VFO signal having a length of time corresponding to a difference in phase between an wobble address phase signal and a data phase reference pulse. The inserting section thus provides a data stream DST consisting of the VFO signals and the data block streams. An LD uses light beams to record the data stream on an optical disk.Type: ApplicationFiled: December 22, 2004Publication date: June 30, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshihiko Kaneshige, Koichi Otake, Hideyuki Yamakawa, Yukiyasu Tatsuzawa, Hiroyuki Moro
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Publication number: 20050141378Abstract: A disk apparatus has an equalizing unit which performs PR equalization for the read signal from the disk based on a plurality of tap coefficients, a decoding unit which performs a decoding process for the equalized read signal, a calculating unit which obtains an ideal signal of the decoded read signal, and compares the ideal signal with the decoded read signal, thereby calculating an error signal E, and a control unit which groups the tap coefficients into at least a first and second coefficient groups which are groups of tap coefficients at symmetrical locations each, and determines tap coefficients of the first coefficient group in a range of a first limit value K1 according to the calculated error signal, determines tap coefficients of the second coefficient group in a range of a second limit value and supplies the determined tap coefficients to the equalizing unit.Type: ApplicationFiled: December 15, 2004Publication date: June 30, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Yukiyasu Tatsuzawa, Koichi Otake, Hideyuki Yamakawa, Hiroyuki Moro, Toshihiko Kaneshige
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Publication number: 20050117484Abstract: A disk device includes a reading section which reads reflected light and outputs a read signal according to the read reflected light, a processing section which calculates an adjustment value from the read signal, performs predetermined processing on the read signal based on the adjustment value, and outputs a process signal, a detecting section which detects a reading defect in the reading section based on the read signal, a determining section which determines signal quality of the process signal output from the processing section, a storage section which stores the adjustment value calculated by the processing section, in a memory area, based on a result output from the determining section, and a controller which, when the detecting section detects the reading defect, performs control so that the adjustment value is read out of the storage section and is supplied to the processing section.Type: ApplicationFiled: November 23, 2004Publication date: June 2, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukiyasu Tatsuzawa, Koichi Otake, Hideyuki Yamakawa, Hiroyuki Moro, Toshihiko Kaneshige
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Publication number: 20050105440Abstract: A disk apparatus has a reading portion which reads out a plurality of frames stored in a disk and outputs a read signal, a detecting portion which determines that part of the read signal is identical to a frame synchronization code signal or determines that a deviation between a symbol of part of the read signal and a symbol of the frame synchronization code signal is within a certain time range to detect the frame synchronization code signals from the read signal, and a reproducing portion which reproduces the read signal in synchronization with the detected frame synchronization code signals.Type: ApplicationFiled: November 18, 2004Publication date: May 19, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Koichi Otake, Hideyuki Yamakawa, Yukiyasu Tatsuzawa, Hiroyuki Moro, Toshihiko Kaneshige
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Patent number: 6769087Abstract: When system data is written to a flash memory, first and second ECCs are generated in correspondence with the system data and its copied data. The system data and the copied data are written to the same page. The first and second ECCs are stored in the redundant area of the page. In this data storage format, even when an uncorrectable bit error occurs in one of the system data and the copied data, correct data can be read out using the other data in which the error does not occur. Since the system data and the copied data are stored in the same page, they can be read out by one operation and thus the operation performance does not deteriorate.Type: GrantFiled: April 9, 2001Date of Patent: July 27, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyuki Moro, Takayoshi Fushinuki
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Publication number: 20040107316Abstract: A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.Type: ApplicationFiled: August 26, 2003Publication date: June 3, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Moro
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Publication number: 20030056050Abstract: An interface unit corresponding to a data pin of an SD memory card comprises a reception buffer having a lead-through current preventing function. The card interface controller validates the lead-through current preventing function when the SD 1-bit mode or SPI mode in which the data lines are not used is designated by a command from a host controller, and invalidates the lead-through current preventing function when the SD 4-bit mode is designated. The safety of the card device is enhanced, and wasteful power consumption is saved.Type: ApplicationFiled: September 5, 2002Publication date: March 20, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Hiroyuki Moro
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Publication number: 20010028523Abstract: When system data is written to a flash memory, first and second ECCs are generated in correspondence with the system data and its copied data. The system data and the copied data are written to the same page. The first and second ECCs are stored in the redundant area of the page. In this data storage format, even when an uncorrectable bit error occurs in one of the system data and the copied data, correct data can be read out using the other data in which the error does not occur. Since the system data and the copied data are stored in the same page, they can be read out by one operation and thus the operation performance does not deteriorate.Type: ApplicationFiled: April 9, 2001Publication date: October 11, 2001Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyuki Moro, Takayoshi Fushinuki