Abstract: A predictor interactive learning system of the present invention includes machine learning unit configured to perform machine learning of a predictor that outputs a predicted value indicating a likelihood of being a predetermined intrinsic expression, by using teacher data and teacher labels, an interest score calculation unit configured tip obtain an interest score according to statistical data of a corresponding word in a corpus including the predicted value of the predictor for each of words of the corpus, an interactive learning frame unit configured to extract the word serving as the teacher data used in next learning of the predictor according to the interest score, and a question-response unit configured to output a question of whether the extracted teacher data is an intrinsic expression of which the likelihood is predicted by the predictor, and to acquire a teacher label corresponding to the teacher data, as a response to the question, in which the machine learning unit performs machine learning of t

Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.

Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.

Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.

Abstract: A communicating hole, which communicates between a clearance space and the outside of a cover member, is formed in the cover member, and a seal cap is fitted to and retained in a distal-end opening of the communicating hole. The seal cap includes a cap main body having a ventilation through hole formed in an internal axial direction and an outer peripheral wall configured to engage with the communicating hole, a supporting portion fitted, from the outside, into a recessed groove formed in an outside end face of the cap main body, and a ventilation filter located on a bottom face of the recessed groove and retained and sandwiched between the cap main body and the supporting portion. Therefore, an internal pressure rise in the clearance space between the cover member and an electric motor can be effectively suppressed, and thus improved mountability and retainability can be obtained.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.

Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.

Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.

Abstract: A valve-timing control apparatus varies a relative phase between a cam shaft and a crankshaft by energizing an electric motor through a power-feeding brush provided to be in contact with a slip ring. The valve-timing control apparatus includes a retaining member slidably retaining the power-feeding brush; a connector provided in the retaining member and connected to a power source; a pigtail harness including one end portion connected with the power-feeding brush, and another end portion connected with a terminal of the connector through a fixing portion; and a guide portion provided in the retaining member and including an outer circumferential surface formed in an arc-shape. The pigtail harness bends along the outer circumferential surface of the guide portion. The another end portion extends substantially in a linear arrangement from the fixing portion to a bending portion at which the pigtail harness bends along the outer circumferential surface.

Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.

Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory including a cache area, and a memory controller. The memory controller sets the available amount of the cache area in response to a first command from the host. In a case where the available amount of the cache area is successfully set, the memory controller transmits a setting completion notification to the host. In a case where the available amount of the cache area cannot be set, the memory controller transmits a notification of non-settable to the host.

Abstract: A method of manufacturing a lens array plate includes: forming a light shielding film on a flat surface of a dielectric substrate; forming a plurality of convex lenses on the flat surface of the dielectric substrate by press molding the dielectric substrate with the light shielding film; and forming a stack of two lens array plates manufactured by press molding. The light shielding film is not formed in a lens formation area in which the convex lens is formed.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.

Abstract: A valve-timing control apparatus varies a relative phase between a cam shaft and a crankshaft by energizing an electric motor through a power-feeding brush provided to be in contact with a slip ring. The valve-timing control apparatus includes a retaining member slidably retaining the power-feeding brush; a connector provided in the retaining member and connected to a power source; a pigtail harness including one end portion connected with the power-feeding brush, and another end portion connected with a terminal of the connector through a fixing portion; and a guide portion provided in the retaining member and including an outer circumferential surface formed in an arc-shape. The pigtail harness bends along the outer circumferential surface of the guide portion. The another end portion extends substantially in a linear arrangement from the fixing portion to a bending portion at which the pigtail harness bends along the outer circumferential surface.

Abstract: A variable valve operating apparatus including an electric motor including a motor housing with a permanent magnet, and a speed reducing mechanism having a casing, the motor housing and the casing of the speed reducing mechanism being coupled to each other by a plurality of bolts, wherein the motor housing includes a convex portion formed in a portion of the motor housing which is opposed to one axial end of the permanent magnet, the convex portion having a threaded hole into which a tip end portion of each bolt is screwed, and a projection formed on an axial end surface of the convex portion in alignment with the threaded hole in an axial direction of the threaded hole, and wherein the axial end surface of the convex portion is located further spaced from the one axial end of the permanent magnet than the projection.

Abstract: A valve-timing control apparatus includes a phase change mechanism configured to change a valve timing, a cover member provided near a front end side of the phase change mechanism; slip rings provided to one of a front end portion of the phase change mechanism and a facing surface of the cover member which faces the phase change mechanism; a pair of brushes provided to another of the front end portion of the phase change mechanism and the facing surface of the cover member to be axially slidable. One end portion the pigtail harness is connected with the corresponding brush. Another end portion of the pigtail harness is connected with a connector terminal under a deflected state, at a location radially shifted from an axis of the corresponding brush. The another end portions of the pair of pigtail harnesses are separated from each other by a partition wall.