Patents by Inventor Hiroyuki Ode

Hiroyuki Ode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066586
    Abstract: According to one embodiment, a semiconductor memory device includes: a first and a second wirings; a third wiring disposed between them; a first phase change layer disposed between the first and the third wirings; a first conducting layer disposed on a first wiring side surface of the first phase change layer; a second conducting layer disposed on a third wiring side surface of the first phase change layer; a second phase change layer disposed between the third and the second wirings; a third conducting layer disposed on a third wiring side surface of the second phase change layer; and a fourth conducting layer disposed on a second wiring side surface of the second phase change layer. The first and the fourth conducting layers have coefficients of thermal conductivity larger or smaller than the coefficients of thermal conductivity of the second and the third conducting layers.
    Type: Application
    Filed: March 5, 2020
    Publication date: March 4, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Hiroyuki ODE
  • Publication number: 20210043559
    Abstract: According to one embodiment, a semiconductor memory device includes: a substrate including a first area, a second area, and a third area, the second and the third areas being adjacent to the first area; a first insulating layer disposed in the first to the third areas; a first wiring disposed on a surface of the first insulating layer in the first area; a first memory cell disposed on the first wiring; a second wiring disposed on the first memory cell; and a contact connected to the second wiring in the second area. The surface of the first insulating layer includes: first surfaces disposed in at least one of the second area and the third area and arranged in the first direction; and second surfaces disposed between the first surfaces. The second surfaces are close to or far from the substrate compared with the first surfaces.
    Type: Application
    Filed: March 5, 2020
    Publication date: February 11, 2021
    Applicant: Kioxia Corpoation
    Inventor: Hiroyuki ODE
  • Publication number: 20210036218
    Abstract: According to one embodiment, a semiconductor memory device includes a first electrode and a second electrode, a phase change layer disposed between the first electrode and the second electrode, and a conducting layer disposed between the first electrode and the phase change layer. The phase change layer contains a crystal having a Face-Centered Cubic lattice structure with a first lattice constant. The conducting layer contains a crystal having a Face-Centered Cubic lattice structure with a second lattice constant. The second lattice constant is larger than 80% and smaller than 120% of the first lattice constant.
    Type: Application
    Filed: March 5, 2020
    Publication date: February 4, 2021
    Applicant: Kioxia Corporation
    Inventor: Hiroyuki ODE
  • Patent number: 10211259
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Oga, Mutsumi Okajima, Natsuki Fukuda, Takeshi Yamaguchi, Toshiharu Tanaka, Hiroyuki Ode
  • Patent number: 10074694
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Patent number: 9905759
    Abstract: According to one embodiment, a memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Publication number: 20170373119
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
    Type: Application
    Filed: March 21, 2017
    Publication date: December 28, 2017
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi OGA, Mutsumi OKAJIMA, Natsuki FUKUDA, Takeshi YAMAGUCHI, Toshiharu TANAKA, Hiroyuki ODE
  • Patent number: 9721961
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi Okajima, Atsushi Oga, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Patent number: 9704922
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Oga, Mutsumi Okajima, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Publication number: 20170117039
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory cell array; and a control circuit that manages a setting operation and a read operation. The memory cell array comprises: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell including a variable resistance element and a nonlinear element. The variable resistance element is configured having a first metal film, a first variable resistance film, a second variable resistance film, and a second metal film stacked and disposed therein in this order. A work function of the second metal film is smaller than a work function of the first metal film.
    Type: Application
    Filed: March 15, 2016
    Publication date: April 27, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi YAMAGUCHI, Takeshi TAKAGI, Hiroyuki ODE, Toshiharu TANAKA
  • Publication number: 20170062713
    Abstract: According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Patent number: 9559300
    Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Ode, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
  • Publication number: 20170025475
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Application
    Filed: February 8, 2016
    Publication date: January 26, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Publication number: 20160351628
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi OKAJIMA, Atsushi OGA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
  • Publication number: 20160351624
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi OGA, Mutsumi OKAJIMA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
  • Patent number: 9418737
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Publication number: 20160189776
    Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.
    Type: Application
    Filed: July 30, 2015
    Publication date: June 30, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi TAKAGI, Masaki YAMATO, Hiroyuki ODE, Takeshi YAMAGUCHI, Toshiharu TANAKA
  • Patent number: 9336880
    Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: May 10, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takeshi Takagi, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Publication number: 20160019959
    Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.
    Type: Application
    Filed: March 2, 2015
    Publication date: January 21, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Masaki Yamato, Hiroyuki Ode, Takeshi Yamaguchi, Toshiharu Tanaka
  • Patent number: 9224878
    Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: December 29, 2015
    Assignees: Intermolecular, Inc., Elpida Memory, Inc.
    Inventors: Sandra G. Malhotra, Hanhong Chen, Wim Deweerd, Arthur Gevondyan, Hiroyuki Ode