Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.

Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory cell array; and a control circuit that manages a setting operation and a read operation. The memory cell array comprises: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell including a variable resistance element and a nonlinear element. The variable resistance element is configured having a first metal film, a first variable resistance film, a second variable resistance film, and a second metal film stacked and disposed therein in this order. A work function of the second metal film is smaller than a work function of the first metal film.

Abstract: According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.

Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.

Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.

Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.

Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.

Abstract: A nonvolatile semiconductor memory device includes: a memory cell array; and a control circuit that controls a voltage applied to this memory cell array. The memory cell array includes: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell disposed at an intersection of these lines and including a variable resistance element. In a rewrite operation of the memory cell, the control circuit repeatedly perform a pulse application operation and a verify operation, the pulse application operation applying a pulse voltage to the memory cell, and the verify operation applying a first voltage to the memory cell to determine whether the rewrite operation has been completed or not. The control circuit is configured to, in a read operation from the memory cell, apply a second voltage to the memory cell. The second voltage has a voltage value larger than the first voltage.

Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.

Abstract: A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.

Abstract: Provided are MIM DRAM capacitors and methods of forming thereof. A MIM DRAM capacitor may include an electrode layer formed from a high work function material (e.g., greater than about 5.0 eV). This layer may be used to reduce the leakage current through the capacitor. The capacitor may also include another electrode layer having a high conductivity base portion and a conductive metal oxide portion. The conductive metal oxide portion serves to promote the growth of the high k phase of the dielectric layer.

Abstract: According to an embodiment, a nonvolatile memory device includes a first wiring extending to a first direction, a second wiring disposed on the first wiring in a second direction which is orthogonal to the first direction, a first insulating film provided between the first wiring and the second wiring, a bit line extending in the second direction, and a variable resistance film contacting an end portion of the first wiring, an end portion of the second wiring, and an end portion of the first insulating film. A dielectric constant of a center portion between the first and second wirings in the second direction is higher than at vicinities of the first and the second wirings. The variable resistance film is disposed between the bit line and the first wiring, between the bit line and the second wiring, and between the bit line and the first insulating film.

Abstract: According to one embodiment, a resistance change element includes: a first electrode; a second electrode; and a resistance change film provided between the first electrode and the second electrode, and the resistance change film including: a first transition metal oxide-containing layer; a second transition metal oxide-containing layer; and an intermediate layer provided between the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, the intermediate layer having a higher crystallization temperature than the first transition metal oxide-containing layer and the second transition metal oxide-containing layer, and the intermediate layer including an amorphous material.

Abstract: A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

Abstract: A memory device according to an embodiment, includes a selection element, a first interconnection provided in a first direction when viewed from the selection element and extending in the first direction, a plurality of second interconnections provided in a second direction crossing the first direction when viewed from the first interconnection and arranged in the first direction, a memory element provided between the first interconnection and the second interconnection, and a high resistance component connected between the selection element and the first interconnection and having a resistivity higher than a resistivity of the first interconnection and a resistivity of the second interconnection.

Abstract: In accordance with an embodiment, a semiconductor memory device includes a substrate, first and second wirings on the substrate across each other, and a storage element at an intersection of the first and second wirings between the first and second wirings. The storage element includes first and second electrodes having first and second materials, respectively, a first film having a first dielectric constant, and a second film having a second dielectric constant lower than the first dielectric constant. The first film is formed on the first electrode. The second electrode is formed on the first film. The second film is disposed between the second electrode and the first film. An energy difference between a vacuum level and a Fermi level of the second material is equal to or more than an energy difference between the vacuum level and a Fermi level of the first material.

Abstract: A semiconductor device comprises a conductor film and a capacitor comprising a lower electrode provided on the conductor film. The conductor film includes a first conductive film containing a first metal, a second conductive film containing a second metal on the first conductive film, and an oxide film of the second metal on the second conductive film. The oxide film of the second metal has a lower electric resistivity than an oxide film of the first metal.