Patents by Inventor Hiroyuki Okuyama

Hiroyuki Okuyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020171089
    Abstract: A display unit and semiconductor light emitting devices are provided. The display unit includes a number of the semiconductor light emitting devices arrayed on a base body, wherein each of the semiconductor light emitting devices is formed together with dummy devices for setting an emission wavelength of the semiconductor light emitting device, and the semiconductor light emitting device is formed by selective growth, and one conductive layer is formed in self-alignment on planes grown from tilt planes formed by selective growth. Such a display unit has a structure suitable for multi-colors without increasing the number of production steps.
    Type: Application
    Filed: March 6, 2002
    Publication date: November 21, 2002
    Inventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Toyoharu Oohata, Masaru Minami
  • Publication number: 20020145150
    Abstract: Semiconductor light emitting devices are provided. The semiconductor light emitting device includes a base body, a selection mask having a stripe-shaped opening portion, the selection mask being formed on the base body, a semiconductor layer formed by selective growth from the opening portion in such a manner as to have a ridge line substantially parallel to long-sides of the opening portion, and a first conductive type cladding layer, an active layer, and a second conductive type cladding layer, which are formed on the semiconductor layer.
    Type: Application
    Filed: March 5, 2002
    Publication date: October 10, 2002
    Inventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Toyoharu Oohata
  • Publication number: 20020145148
    Abstract: Semiconductor light emitting devices and methods of producing same are provided. The semiconductor light emitting devices include a substrate that has a surface including a difference-in-height portion composed of, for example, a wurtzite compound. A crystal growth layer is formed in the substrate surface wherein at least a portion of which is oriented along an inclined plane with respect to a principal plane of the substrate. The semiconductor device includes a first conductive layer, an active layer and a second conductive layer formed on the crystal layer in a stacked arrangement and oriented along the inclined place.
    Type: Application
    Filed: December 17, 2001
    Publication date: October 10, 2002
    Inventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Toyoharu Oohata
  • Patent number: 6462354
    Abstract: There are provided a semiconductor light emitting device using high-quality and high-performance nitride III-V compound semiconductors which can reduce the threshold current density and operation voltage, and can shorten the emission wavelength to the ultraviolet range and a semiconductor device using nitride III-V compound semiconductors excellent in electric property and optical property and having a high band gap. In a GaN semiconductor light emitting device, desired layers among a plurality of semiconductor layers forming its light emitting structure are made of nitride III-V compound semiconductors containing B while limiting the B composition not higher than 0.3. More specifically, sequentially stacked on a c-plane sapphire substrate are, via a B0.05Ga0.95N buffer layer, a B0.05Ga0.95N layer, n-type B0.02Al0.03Ga0.95N cladding layer, n-type GaN optical guide layer, active layer having a MQW structure including quantum well layers of Ga0.85In0.15N, p-type B0.1Ga0.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: October 8, 2002
    Assignee: Sony Corporation
    Inventor: Hiroyuki Okuyama
  • Publication number: 20020117677
    Abstract: Semiconductor light-emitting devices are provided. The semiconductor light-emitting devices include a substrate and a crystal layer selectively grown thereon at least a portion of the crystal layer is oriented along a plane that slants to or diagonally intersect a principal plane of orientation associated with the substrate thereby for example, enhancing crystal properties, preventing threading dislocations, and facilitating device miniaturization and separation during manufacturing and use thereof.
    Type: Application
    Filed: January 30, 2002
    Publication date: August 29, 2002
    Inventors: Hiroyuki Okuyama, Masato Doi, Goshi Biwa, Toyoharu Oohata, Tomoyuki Kikutani
  • Patent number: 6429032
    Abstract: In a nitride semiconductor of BpAlqGarInsN (0≦p≦1, 0≦q≦1, 0≦r≦1, 0≦s≦1, p+q+r+s=1), in particular a p-type nitride compound semiconductor, a point defect concentration of the p-type semiconductors is set to 1×1019 cm−3 or more. This makes it possible to obtain a high carrier concentration at room temperature.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: August 6, 2002
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Hiroshi Nakajima, Fumihiko Nakamura
  • Publication number: 20020098607
    Abstract: In a nitride semiconductor of BpAlqGarInsN (0≦p≦1, 0≦q≦1, 0≦r≦1, 0≦s≦1, p+q+r+s=1), in particular a p-type nitride compound semiconductor, a point defect concentration of the p-type semiconductors is set to 1×1019 cm−3 or more. This makes it possible to obtain a high carrier concentration at room temperature.
    Type: Application
    Filed: March 8, 2002
    Publication date: July 25, 2002
    Inventors: Hiroyuki Okuyama, Hiroshi Nakajima, Fumihiko Nakamura
  • Publication number: 20020048909
    Abstract: Disclosed herein is a process for vapor phase growth of gallium nitride compound semiconductor which yields uniform crystal layers with good reproducibility. The process comprises forming a first nitride semiconductor layer on a substrate, forming thereon a protective film for crystal growth prevention in such a way that it has partly open window regions through which the first nitride semiconductor layer is exposed, forming a second nitride semiconductor layer by selective growth from the first nitride semiconductor layer at a crystal growth starting temperature, and continuing crystal growth at a temperature higher than the crystal growth starting temperature. The vapor phase growth at a low temperature yields a uniform crystal layer, and the ensuing vapor phase growth at a raised temperature yields a uniform crystal layer with good reproducibility in conformity with the first crystal layer.
    Type: Application
    Filed: July 31, 2001
    Publication date: April 25, 2002
    Inventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
  • Publication number: 20020043208
    Abstract: A crystal growth method includes forming a mask layer capable of impeding crystal growth on a substrate in such a way a first nitride semiconductor layer has irregularities at a surface thereof exposed at a window region opened at a part of the mask layer, and growing a second nitride semiconductor layer over a region including the surface of the mask layer through crystal growth from the irregularities. Through-type dislocations can be reliably prevented from propagation due to the discontinuity of crystals at the irregularities and also to lateral crystal growth.
    Type: Application
    Filed: July 17, 2001
    Publication date: April 18, 2002
    Inventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
  • Patent number: 6278804
    Abstract: A sampled image data in the form of a matrix is compared with each of the template image data provided in advance for matching and, if they are matched with each other, the coordinate values of the profile spots of each black image component of the sampled image data are determined. Then, the existence of any island-like region containing a set of several pixels (spots within a photograph region) in the sample image data is discriminated on the basis of the number of the profile spots and their correlations. If one or more than one island-like regions exist, the image having the island-like regions subjected to a smoothing operation is not selected but the image data A from the matrix forming section is selected. Thus, there is provided an image processing apparatus with which photograph regions are protected against any unnecessary smoothing operation to eliminate the risk of damaging the quality of the image.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: August 21, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Okuyama
  • Patent number: 6206962
    Abstract: An n-type cladding layer, the first guiding layer, an active layer, the second guiding layer, a p-type cladding layer, a backing layer, a contact layer, a superlattice layer and a cap layer are stacked in this order on an n-type substrate. The cap layer comprises p-type ZnTe and has a thickness of less than 10 nm. The contact layer is comprised of p-type ZnSe and the concentration of nitrogen added to the contact layer is in the range of 1 to 2×1018 cm−3. The backing layer comprises p-type ZnSSe mixed crystal and the concentration of nitrogen added to the backing layer is higher than that of the contact layer, in the range of 1 to 3×1018 cm−3. Before the corresponding Group II-VI compound semiconductor layers are grown by the MBE method, the temperature of cells is once increased.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: March 27, 2001
    Assignee: Sony Corporation
    Inventors: Satoru Kijima, Hiroyuki Okuyama
  • Patent number: 6069367
    Abstract: The purpose of the present invention is to provide a semiconductor light-emitting element that can reduce an operational voltage by improving a contact construction with a p-side electrode. An n-type clad layer, a first guide layer, an active layer, a second guide layer, a p-type clad layer, a ZnSSe cap layer, a ZnSe cap layer, a compositional gradient super-lattice layer, and a low defect contact layer are sequentially laminated on an n-type substrate. The compositional gradient super-lattice layer is formed by alternately laminating p-type ZnTe layers and p-type ZnSe layers. The p-type ZnTe layers are formed to be thickened toward the side of the low defect contact layer. The thickness of the low defect contact layer must be 5 nm or less. Relaxing lattice distortion reduces defect density of the low defect contact layer. Accordingly, the increase in the operational voltage immediately after energization is suppressed, and the operational voltage becomes lower.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: May 30, 2000
    Assignee: Sony Corporation
    Inventors: Shigetaka Tomiya, Satoru Kijima, Hiroyuki Okuyama, Satoshi Taniguchi, Hironori Tsukamoto
  • Patent number: 5872023
    Abstract: The semiconductor light emitting device includes a semiconductor substrate (1), a first conductivity type first cladding layer (2) deposited on the semiconductor substrate (1), an active layer (4) deposited on the first cladding layer (2), and the second conductivity type second cladding layer (6) deposited on the active layer (4). The first and the second cladding layers (2, 6) are made of the II/VI-compound semiconductors including at least one kind of II group elements such as Zn, Hg, Cd, Mg and at least one kind of VI group elements such as S, Se, Te. The lattice mismatching .DELTA.a/a (%) between at least one of the first cladding layer (2) and the second cladding layer (6) and the substrate is set within the range of -0.9%.ltoreq..DELTA.a/a.ltoreq.0.5% (reference symbols a and a.sub.c represent the lattice constant of the semiconductor substrate and the lattice constant of at least either of the first and second cladding layers, and .DELTA.a is obtained from .DELTA.a=a.sub.c -a).
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: February 16, 1999
    Assignee: Sony Corporation
    Inventors: Masashi Shiraishi, Satoshi Ito, Kazushi Nakano, Akira Ishibashi, Masao Ikeda, Hiroyuki Okuyama, Katsuhiro Akimoto, Tomonori Hino, Masakazu Ukita
  • Patent number: 5865897
    Abstract: A film of a II-VI group compound semiconductor of at least one of elements belonging to the II group of the periodic table and at least one of elements belonging to the VI group of the periodic table is deposited on a substrate. When the film is deposited on the substrate, a plasma of nitrogen in an excited state is applied to the substrate while removing charged particles from said plasma by a charged particle removing means. The deposited film of a nitrogen-doped II-VI group compound semiconductor has an increased percentage of activated nitrogen atoms and improved crystallinity.
    Type: Grant
    Filed: February 9, 1996
    Date of Patent: February 2, 1999
    Assignee: Sony Corporation
    Inventors: Satoshi Ito, Satoshi Taniguchi, Masao Ikeda, Hiroyuki Okuyama, Hironori Tsukamoto, Masaharu Nagai, Koshi Tamamura
  • Patent number: 5740193
    Abstract: A II-VI group compound semiconductor light-emitting device can emit light of a short wavelength at room temperature. Operation characteristics, such as current--voltage characteristics and current--light output characteristics can be stabilized and a life of this semiconductor light-emitting device can be extended. The semiconductor light-emitting device comprises a substrate (1), at least a first cladding layer (2) of a first conductivity type, an active layer (3) and a second cladding layer (4) of a second conductivity type, wherein at least the active layer (3) is made of a II-VI group compound semiconductor and the active layer (3) is doped by either or both of n-type and p-type dopants.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: April 14, 1998
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Akira Ishibashi, Eisaku Kato, Hiroshi Yoshida, Kazushi Nakano, Masakazu Ukita, Satoru Kijima, Sakurako Okamoto
  • Patent number: 5657336
    Abstract: A II-VI group compound semiconductor light-emitting device can emit light of a short wavelength at room temperature. Operation characteristics, such as current--voltage characteristics and current--light output characteristics can be stabilized and a life of this semiconductor light-emitting device can be extended. The semiconductor light-emitting device comprises a substrate (1), at least a first cladding layer (2) of a first conductivity type, an active layer (3) and a second cladding layer (4) of a second conductivity type, wherein at least the active layer (3) is made of a II-VI group compound semiconductor and the active layer (3) is doped by either or both of n-type and p-type dopants.
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: August 12, 1997
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Akira Ishibashi, Eisaku Kato, Hiroshi Yoshida, Kazushi Nakano, Masakazu Ukita, Satoru Kijima, Sakurako Okamoto
  • Patent number: 5633514
    Abstract: The semiconductor light emitting device includes a semiconductor substrate (1), a first conductivity type first cladding layer (2) deposited on the semiconductor substrate (1), an active layer (4) deposited on the first cladding layer (2), and the second conductivity type second cladding layer (6) deposited on the active layer (4). The first and the second cladding layers (2, 6) are made of the II/VI-compound semiconductors including at least one kind of group II elements such as Zn, Hg, Cd, Mg and at least one kind of group VI elements such as S, Se, Te. The lattice mismatching .DELTA.a/a (%) between at least one of the first cladding layer (2) and the second cladding layer (6) and the substrate is set within the range of -0.9%.ltoreq..DELTA.Aa/a.ltoreq.0.5% (reference symbols a and a.sub.c represent the lattice constant of the semiconductor substrate and the lattice constant of at least either of the first and second cladding layers, and .DELTA.a is obtained from .DELTA.a=a.sub.c -a).
    Type: Grant
    Filed: December 11, 1995
    Date of Patent: May 27, 1997
    Assignee: Sony Corporation
    Inventors: Masashi Shiraishi, Satoshi Ito, Kazushi Nakano, Akira Ishibashi, Masao Ikeda, Hiroyuki Okuyama, Katsuhiro Akimoto, Tomonori Hino, Masakazu Ukita
  • Patent number: 5582424
    Abstract: An occupant restraint device includes a container having an opening, a lid covering the opening of the container, and an inflatable occupant restraint cushion within the container. The cushion has a cushion portion adjacent the lid. The lid includes a first portion arranged to be first contacted by the inflatable occupant restraint cushion when it inflates and a second portion adjacent to the first portion. The first and second portions are perforated to provide different rupturabilities such that the first portion provides the greatest rupturability.
    Type: Grant
    Filed: January 19, 1995
    Date of Patent: December 10, 1996
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Hiroyuki Okuyama, Kei Iizuka
  • Patent number: 5567960
    Abstract: A lifetime of a II/VI-compound semiconductor light emitting device can be extended. The II/VI-compound semiconductor light emitting device includes an active layer (4) and a p-side cladding layer (6). An active-layer side portion (26) of the p-side cladding layer (6) is formed as a lightly impurity-doped region or a non-doped region.
    Type: Grant
    Filed: April 27, 1995
    Date of Patent: October 22, 1996
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Satoshi Ito, Hiroyuki Okuyama, Kazushi Nakano, Kenji Kondo, Reiko Takeishi
  • Patent number: 5515393
    Abstract: A semiconductor laser using a II-VI compound semiconductor as the material for cladding layers, capable of emitting a blue to green light is disclosed. In an aspect of the semiconductor laser, an n-type ZnSe buffer layer, an n-type ZnMgSSe cladding layer, an active layer made of, for example, ZnCdSe, a p-type ZnMgSSe cladding layer and a p-type ZnSe contact layer are stacked in sequence on an n-type GaAs substrate. A p-side electrode such as an Au/Pd electrode is provided in contact with the p-type ZnSe contact layer. An n-side electrode such as an In electrode is provided on the back surface of the n-type GaAs substrate. In another aspect of the semiconductor laser, an n-type optical guiding layer made of ZnSSe, ZnMgSSe or ZnSe is provided between the n-type ZnMgSSe cladding layer and the active layer, and a p-type optical guiding layer made of ZnSSe, ZnMgSSe or ZnSe is provided between the p-type ZnMgSSe cladding layer and the active layer.
    Type: Grant
    Filed: August 4, 1993
    Date of Patent: May 7, 1996
    Assignee: Sony Corporation
    Inventors: Hiroyuki Okuyama, Katsuhiro Akimoto, Takao Miyajima, Masafumi Ozawa, Yuko Morinaga, Futoshi Hiei, Kazushi Nakano, Toyoharu Ohata