Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.

Abstract: A semiconductor device has first conductivity type regions extending in a first direction, and second conductivity type regions extending in the first direction. The first conductivity type regions and the second conductivity type regions are alternately arranged in a second direction perpendicular to the first direction. The semiconductor device includes a first impurity diffused regions formed in the first conductivity type regions, a first local wiring connected to the first conductivity type regions, and extending in the second direction, a first potential supply wiring formed above the first local wiring, and extending in the first direction, and a first contact hole for connecting the first local wiring to the first potential supply wiring.

Abstract: There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

Abstract: There is provided a layout structure of a semiconductor integrated circuit capable of preventing the thinning of a metal wiring line close to a cell boundary and wire breakage therein without involving increases in the amount of data for OPC correction and OPC process time. In a region interposed between a power supply line and a ground line each placed to extend in a first direction, first and second cells each having a transistor and an intra-cell line each for implementing a circuit function are placed to be adjacent to each other in the first direction. In a boundary portion between the first and second cells, a metal wiring line extending in a second direction orthogonal to the first direction is placed so as not to short-circuit the power supply line and the ground line.

Abstract: In a layout structure of a semiconductor integrated circuit, when transistors are arranged in a constant gate wiring pitch, a common source diffusion region is provided between two adjacent transistors, a CA via is provided on the common source diffusion region, and a source wiring connected to the CA via is provided on the common source diffusion region. An inter-drain wiring connecting the drain regions of the two transistors is formed in a wiring layer higher than the source wiring. Therefore, the wiring path of the source wiring is not limited by the wiring path of the inter-drain wiring, and can be provided, covering the common source diffusion region to a further extent. As a result, the number of high-resistance CA vias or the flexibility of arrangement is increased, leading to a reduction in source resistance, resulting in an increase in operating speed of the semiconductor integrated circuit.

Abstract: In a standard cell in which a substrate voltage control technique is implemented, a plurality of normal power supply wires are disposed at previously set positions. Therefore, when the standard cell is disposed adjacent to another standard cell having such normal power supply wires, these normal power supply wires are connected to each other. In addition, the standard cell is provided with a substrate power supply terminal which is not connected to that of the other standard cell when the other standard cell is disposed adjacent to the standard cell. Therefore, when a semiconductor integrated circuit is composed of a plurality of the standard cells, a wiring route of an inter-cell substrate power supply wire, or the like can be freely set.

Abstract: To obtain a delay circuit which does not involve an increase in a circuit area occupied by load transistors even when the number of inverters is increased, an integrated circuit device has four series-connected inverters 101 and two load transistors 104, 105, and is configured such that the A VDD source current to be consumed by all of the inverters 101 is supplied by way of the load transistor 104 and such that a VSS source current to be consumed by all of inverters 1010 is supplied by way of the other load transistor 105.