Patents by Inventor Hiroyuki Tsujikawa

Hiroyuki Tsujikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6303251
    Abstract: In order that CAD processing time required for modifying an input design pattern to compensate for optical proximity effects is reduced, increases in the number of base shapes when corrected data are converted into EB data are restricted, and false detection of defects in a photomask inspection process is restricted, the following steps are taken. At a shape selection step, rectangular shapes are divided into a dense rectangular shape group and a non-dense rectangular shape group according to the distance of each rectangular shape to an adjacent rectangular shape. At a number-of-shapeas comparison step, the number of shapes included in the dense rectangular shape group is compared to the number of shapes included in the non-dense rectangular shape group to select either shape group for correction. At a correction process selection step, a correction process suited for the selected shape group is selected. At a shape correction step, optical proximity correction is made.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: October 16, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyohito Mukai, Hidenori Shibata, Hiroyuki Tsujikawa
  • Patent number: 6183920
    Abstract: A semiconductor device geometrical pattern correction process, semiconductor device manufacturing process and geometrical pattern extraction process are provided, which make it possible to eliminate the adverse effect of corner rounding accompanying miniaturization, that is, a decrease in the projection amount of a gate, while avoiding increased chip area. The correction process comprises a step 102 of detecting a concave diffusion layer corresponding portion and a step 103 of correcting either the concave diffusion layer corresponding portion or a transistor gate corresponding portion which projects from the concave diffusion layer corresponding portion in order to ensure the projection of the gate from the concave diffusion layer corresponding portion against possible corner rounding.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: February 6, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Tsujikawa, Hidenori Shibata, Kiyohito Mukai