Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: A semiconductor device includes a lower insulating layer on a lower substrate, a lower pad structure inside the lower insulating layer, an upper insulating layer on the lower insulating layer, an upper pad structure inside the upper insulating layer, and an upper substrate on the upper insulating layer. A via plug passes through at least a portion of each of the upper substrate, the upper insulating layer, and the lower insulating layer, and in contact with the upper pad structure and the lower pad structure. The upper pad structure includes upper pad conductive layers and an upper connection layer between the upper pad conductive layers. The upper connection layer includes a conductive pattern having a shape different from a shape of at least one of the upper pad conductive layers. The via plug is in direct contact with the upper pad conductive layers and the upper connection layer.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.

Abstract: A semiconductor device includes a lower insulating layer on a lower substrate, a lower pad structure inside the lower insulating layer, an upper insulating layer on the lower insulating layer, an upper pad structure inside the upper insulating layer, and an upper substrate on the upper insulating layer. A via plug passes through at least a portion of each of the upper substrate, the upper insulating layer, and the lower insulating layer, and in contact with the upper pad structure and the lower pad structure. The upper pad structure includes upper pad conductive layers and an upper connection layer between the upper pad conductive layers. The upper connection layer includes a conductive pattern having a shape different from a shape of at least one of the upper pad conductive layers. The via plug is in direct contact with the upper pad conductive layers and the upper connection layer.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor is provided that includes a substrate including a first surface, a second surface facing the first surface, and a first recess region that is recessed from the first surface toward the second surface. The CMOS image sensor further includes a transfer gate on the substrate, and a source follower gate on the first recess region. The source follower gate is within the first recess region and partially covers a portion of the first surface of the substrate.

Abstract: An image sensor including first and second pixel regions adjacent to each other in a first direction in a light-receiving region that receives light and generates charges; a third pixel region adjacent to the first pixel region in a second direction intersecting the first direction in the light-receiving region; a first device isolation layer between the first and second pixel regions and between the first and third pixel regions to separate the first pixel region from the second pixel region and the first pixel region from the third pixel region; second device isolation layers in each of the first to third pixel regions to define active regions; a plurality of transfer gates and a plurality of logic gates on the active regions; and a side connection contact overlapping the first device isolation layer and connected to a side surface of an active region.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: An image sensor including first and second pixel regions adjacent to each other in a first direction in a light-receiving region that receives light and generates charges; a third pixel region adjacent to the first pixel region in a second direction intersecting the first direction in the light-receiving region; a first device isolation layer between the first and second pixel regions and between the first and third pixel regions to separate the first pixel region from the second pixel region and the first pixel region from the third pixel region; second device isolation layers in each of the first to third pixel regions to define active regions; a plurality of transfer gates and a plurality of logic gates on the active regions; and a side connection contact overlapping the first device isolation layer and connected to a side surface of an active region.

Abstract: A device includes a substrate and a plurality of unit pixels disposed in and/or on the substrate, arranged in a honeycomb pattern and separated from one another by a deep trench isolation (DTI) layer. The plurality of unit pixels may include a group of unit pixels radially arranged around and equidistant from a central unit pixel.

Abstract: A complementary metal oxide semiconductor (CMOS) image sensor is provided that includes a substrate including a first surface, a second surface facing the first surface, and a first recess region that is recessed from the first surface toward the second surface. The CMOS image sensor further includes a transfer gate on the substrate, and a source follower gate on the first recess region. The source follower gate is within the first recess region and partially covers a portion of the first surface of the substrate.

Abstract: An image sensor includes a lower substrate including logic circuits and an upper substrate including pixels. Transistors provided on the upper substrate have the same conductivity type. Each of the transistors includes source/drain regions provided in the upper substrate, an upper gate electrode provided on the upper substrate, and a silicon oxide layer disposed between the upper substrate and the upper gate electrode. The silicon oxide layer is in physical contact with the upper substrate and the upper gate electrode.

Abstract: Image sensors are provided including a substrate defining a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface. The second surface of the substrate is configured to receive light incident thereon and the substrate defines a deep trench extending from the second surface of the substrate toward the first surface substrate and separating the plurality of pixel regions from each other. In each of the plurality of pixel regions of the substrate, a photoelectric conversion region is provided. A gate electrode is provided on the photoelectric conversion region and a negative fixed charge layer covering the second surface of the substrate and at least a portion of a sidewall of the deep trench is also provided. The image sensors further include a shallow device isolation layer on the first surface of the substrate.

Abstract: A device includes a substrate and a plurality of unit pixels disposed in and/or on the substrate, arranged in a honeycomb pattern and separated from one another by a deep trench isolation (DTI) layer. The plurality of unit pixels may include a group of unit pixels radially arranged around and equidistant from a central unit pixel.

Abstract: Image sensors are provided including a substrate defining a plurality of pixel regions, the substrate having a first surface and a second surface opposite the first surface. The second surface of the substrate is configured to receive light incident thereon and the substrate defines a deep trench extending from the second surface of the substrate toward the first surface substrate and separating the plurality of pixel regions from each other. In each of the plurality of pixel regions of the substrate, a photoelectric conversion region is provided. A gate electrode is provided on the photoelectric conversion region and a negative fixed charge layer covering the second surface of the substrate and at least a portion of a sidewall of the deep trench is also provided. The image sensors further include a shallow device isolation layer on the first surface of the substrate.

Abstract: A CMOS image sensor has a photodiode including first and second impurity layers sequentially formed on a substrate, an isolation layer on the second impurity layer, and a transfer gate structure through the second impurity layer. The transfer gate structure contacts a top surface of the first impurity layer and a portion of the second impurity layer and includes a bottom surface having a step shape.