Patents by Inventor Hisao Hayashi
Hisao Hayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240123467Abstract: A method for coating a vehicle body on which an electrodeposition coating has been performed includes in this order: applying a first base coating material over an outer surface of the vehicle body to form a first base layer; applying a mixture of a second base coating material and a first curing agent over an inner surface of the vehicle body to form an inner second base layer; applying the second base coating material over the first base layer that has not been baked to form an outer second base layer; applying a clear coating material over the inner second base layer and the outer second base layer to form a clear layer; and baking the first base layer, the inner second base layer, the outer second base layer, and the clear layer for curing thereof.Type: ApplicationFiled: October 4, 2023Publication date: April 18, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Keiji AMBO, Junya OGAWA, Hisao HAYASHI
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Patent number: 9943878Abstract: A coating method for forming a laminated coating film including a lower layer formed on a base material and an upper layer formed on the lower layer including: preparing a thermosetting coating material as a lower layer-coating material and preparing a thermosetting coating material as an upper layer-coating material; forming an uncured laminated coating film by applying the lower layer-coating material and the upper layer-coating material on the base material using a wet-on-wet technique; and simultaneously curing the lower layer-coating material and the upper layer-coating material by baking the uncured laminated coating film. In the preparation step, the lower layer-coating material and the upper layer-coating material are selected so that an absolute value of a difference in shrinkage ratio between the lower layer and the upper layer coating materials is 2.0% or smaller at a late stage of the baking step.Type: GrantFiled: December 12, 2014Date of Patent: April 17, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuji Yomo, Kazuyuki Tachi, Hisao Hayashi
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Patent number: 9931669Abstract: A coating method for forming a laminated coating film including: preparing a thermosetting coating material as a lower layer-coating material, an intermediate layer-coating material, and as an upper layer-coating material; forming an uncured laminated coating film by applying the lower layer-coating, the intermediate layer-coating, and the upper layer-coating materials on the base material using a wet-on-wet technique; and simultaneously curing the lower layer-coating, the intermediate layer-coating, and upper layer-coating materials by baking the uncured laminated coating film.Type: GrantFiled: December 12, 2014Date of Patent: April 3, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuji Yomo, Kazuyuki Tachi, Hisao Hayashi
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Publication number: 20170036240Abstract: A coating method for forming a laminated coating film including a lower layer formed on a base material and an upper layer formed on the lower layer including: preparing a thermosetting coating material as a lower layer-coating material and preparing a thermosetting coating material as an upper layer-coating material; forming an uncured laminated coating film by applying the lower layer-coating material and the upper layer-coating material on the base material using a wet-on-wet technique; and simultaneously curing the lower layer-coating material and the upper layer-coating material by baking the uncured laminated coating film. In the preparation step, the lower layer-coating material and the upper layer-coating material are selected so that an absolute value of a difference in shrinkage ratio between the lower layer and the upper layer coating materials is 2.0% or smaller at a late stage of the baking step.Type: ApplicationFiled: December 12, 2014Publication date: February 9, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuji YOMO, Kazuyuki TACHI, Hisao HAYASHI
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Publication number: 20170036244Abstract: A coating method for forming a laminated coating film including: preparing a thermosetting coating material as a lower layer-coating material, an intermediate layer-coating material, and as an upper layer-coating material; forming an uncured laminated coating film by applying the lower layer-coating, the intermediate layer-coating, and the upper layer-coating materials on the base material using a wet-on-wet technique; and simultaneously curing the lower layer-coating, the intermediate layer-coating, and upper layer-coating materials by baking the uncured laminated coating film.Type: ApplicationFiled: December 12, 2014Publication date: February 9, 2017Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Shuji YOMO, Kazuyuki TACHI, Hisao HAYASHI
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Patent number: 8779417Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.Type: GrantFiled: October 28, 2013Date of Patent: July 15, 2014Assignee: Sony CorporationInventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
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Publication number: 20140048814Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.Type: ApplicationFiled: October 28, 2013Publication date: February 20, 2014Applicant: SONY CORPORATIONInventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
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Patent number: 8604483Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.Type: GrantFiled: June 25, 2010Date of Patent: December 10, 2013Assignee: Sony CorporationInventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
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Patent number: 8558981Abstract: Disclosed herein is a display device including a pair of substrates opposed to each other, a pixel region provided between the substrates, and an external wiring provided on an extension of one of the substrates. The external wiring is disposed in a recess formed on the extension. With this structure, the external wiring provided on the extension can be reliably protected to thereby improve the reliability of the display device.Type: GrantFiled: June 30, 2008Date of Patent: October 15, 2013Assignee: Japan Display West, Inc.Inventors: Hisao Hayashi, Shigetaka Toriyama
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Patent number: 8546200Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.Type: GrantFiled: October 18, 2012Date of Patent: October 1, 2013Assignee: Sony CorporationInventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
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Publication number: 20100264422Abstract: A thin film semiconductor device formed as integrated circuits on an insulating substrate with bottom gate type thin film transistors stacked with gate electrodes, a gate insulating film and a semiconductor thin film in the order from below upward. The gate electrodes comprise metallic materials with thickness less than 100 nm. The gate insulating film has a thickness thicker than the gate electrodes. The semiconductor thin film comprises polycrystalline silicon crystallized by a laser beam. By reducing thickness of metallic gate electrodes, thermal capacity becomes small and difference in thermal condition on the metallic gate electrodes and on the insulating substrate made of glass or the like becomes small. This invention relates to the task of uniforming and optimizing recrystallization by a laser anneal treatment provided for the semiconductor thin film which works as an active layer of the bottom gate type thin film transistors.Type: ApplicationFiled: June 25, 2010Publication date: October 21, 2010Applicant: Sony CorporationInventors: Hisao Hayashi, Masahiro Fujino, Yasushi Shimogaichi, Makoto Takatoku
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Publication number: 20080273156Abstract: Disclosed herein is a display device including a pair of substrates opposed to each other, a pixel region provided between the substrates, and an external wiring provided on an extension of one of the substrates. The external wiring is disposed in a recess formed on the extension. With this structure, the external wiring provided on the extension can be reliably protected to thereby improve the reliability of the display device.Type: ApplicationFiled: June 30, 2008Publication date: November 6, 2008Applicant: Sony CorporationInventors: Hisao Hayashi, Shigetaka Toriyama
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Patent number: 7394514Abstract: Disclosed herein is a display device including a pair of substrates opposed to each other, a pixel region provided between the substrates, and an external wiring provided on an extension of one of the substrates. The external wiring is disposed in a recess formed on the extension. With this structure, the external wiring provided on the extension can be reliably protected to thereby improve the reliability of the display device.Type: GrantFiled: April 11, 2005Date of Patent: July 1, 2008Assignee: Sony CorproationInventors: Hisao Hayashi, Shigetaka Toriyama
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Patent number: 7209251Abstract: A management server transfers initial registration information to a registered information memory section of a document input/output apparatus. Upon completion of initial registration, the management server notifies by electronic mail the user's personal computer of the completion of registration, and displays from a www server a handling method and a method of software installation. The management server notifies by electronic mail the user's personal computer of replacement timing of expendables or any hardware trouble.Type: GrantFiled: October 23, 2001Date of Patent: April 24, 2007Assignee: NEC CorporationInventor: Hisao Hayashi
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Patent number: 7006133Abstract: A compact image input apparatus is operable under low power consumption, while omitting a buffer memory for storing image data, which is originally required to transfer image data between this image input apparatus and a personal computer.Type: GrantFiled: March 19, 1999Date of Patent: February 28, 2006Assignee: NEC CorporationInventor: Hisao Hayashi
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Patent number: 6952021Abstract: A bottom-gate thin-film transistor includes a gate electrode, a gate insulating film, an active layer, and a protective insulating film deposited in that order on a substrate. The protective insulating film has a thickness of 100 nm or less, and the protective insulating film is formed on any one of the active layer, and LDD region, and a source-drain region. A method for making a bottom-gate thin-film transistor, a liquid crystal display device including a TFT substrate using the bottom-gate thin-film transistor and a method for fabricating the same, and an organic EL device including the bottom-gate thin-film transistor and a method for fabricating the same are also disclosed.Type: GrantFiled: January 18, 2002Date of Patent: October 4, 2005Assignee: Sony CorporationInventors: Tsutomu Tanaka, Masahiro Fujino, Hisao Hayashi
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Patent number: 6943369Abstract: Substrates suitable to manufacture and products of a thin film semiconductor device are provided, by at first preparing a manufacturing substrate having a characteristic capable of enduring a process for forming a thin film transistor and a product substrate having a characteristic of being suitable to direct mounting of the thin film transistor in a preparatory step, then applying a bonding step to bond the manufacturing substrate to the product substrate for supporting the product substrate at the back, successively applying a formation step to form at least a thin film transistor to the surface of the product substrate in a state reinforced with the manufacturing substrate and, finally, applying a separation step to separate the manufacturing substrate after use from the product substrate.Type: GrantFiled: March 16, 2001Date of Patent: September 13, 2005Assignee: Sony CorporationInventor: Hisao Hayashi
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Patent number: 6933180Abstract: A bottom-gate thin-film transistor includes a gate electrode, a gate insulating film, an active layer, and a protective insulating film deposited in that order on a substrate. The protective insulating film has a thickness of 100 nm or less, and the protective insulating film is formed on any one of the active layer, and LDD region, and a source-drain region. A method for making a bottom-gate thin-film transistor, a liquid crystal display device including a TFT substrate using the bottom-gate thin-film transistor and a method for fabricating the same, and an organic EL device including the bottom-gate thin-film transistor and a method for fabricating the same are also disclosed.Type: GrantFiled: April 6, 2001Date of Patent: August 23, 2005Assignee: Sony CorporationInventors: Tsutomu Tanaka, Masahiro Fujino, Hisao Hayashi
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Publication number: 20050179851Abstract: Disclosed herein is a display device including a pair of substrates opposed to each other, a pixel region provided between the substrates, and an external wiring provided on an extension of one of the substrates. The external wiring is disposed in a recess formed on the extension. With this structure, the external wiring provided on the extension can be reliably protected to thereby improve the reliability of the display device.Type: ApplicationFiled: April 11, 2005Publication date: August 18, 2005Inventors: Hisao Hayashi, Shigetaka Toriyama
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Patent number: 6906830Abstract: The image scanner 101 comprises a manuscript conveying unit 102 having conveying rolls 115, 116 for conveying a manuscript 111 and a first light source 114, and a manuscript reading unit 103 mounted on the manuscript conveying unit 102. The manuscript reading unit 103 detects movement of the manuscript 111 in the sub-scanning direction 118 by a rotation detecting roll 122 driven by the conveying roll 115. When the manuscript 111 is a reflection-type one, only a second light source 124 is switched ON to read the manuscript 111. When the manuscript 111 is a transmission-type one, only the first light source 114 is switched ON to read the manuscript 111. The image scanner 101 does not have a fixed platen. One-dimensional CCD 131 is fixed. The image scanner 101 can therefore be small in size.Type: GrantFiled: January 27, 2000Date of Patent: June 14, 2005Assignee: NEC CorporationInventor: Hisao Hayashi