Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a tunneling insulating film, a floating gate, a leak suppression unit, an inter-gate insulating film, and a control gate. The substrate includes silicon. The tunneling insulating film is provided on the substrate. The floating gate is provided on the tunneling insulating film. The leak suppression unit is provided on the floating gate. The inter-gate insulating film is provided on the leak suppression unit. The control gate is provided on the inter-gate insulating film. The dielectric constant of the leak suppression unit is higher than a dielectric constant of the inter-gate insulating film.

Abstract: A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell transistor obtained by sequentially stacking the gate insulation film, the floating gate electrode, the interelectrode insulation film, and the control gate electrode over the channel semiconductor layer. The control gate electrode has a structure obtained by sequentially stacking the semiconductor film, the silicide phase-change suppressing layer, and the silicide film. In addition, the silicide phase-change suppressing layer includes a polycrystalline silicon film in which at least one of C, F, and N is doped in a concentration range of 1×1020 to 5×1021 [atom/cm3].

Abstract: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

Abstract: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

Abstract: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

Abstract: A semiconductor memory device according to one embodiment includes: a semiconductor substrate having an active region divided by an element isolation region; a plurality of stacked-gate type memory cell transistors connected in series on the active region; select transistors connected to both ends of the plurality of memory cell transistors on the active region; and a bit line contact connected to a drain region belonging to the select transistor in the active region, a vertical cross sectional shape of a lower portion of the bit line contact in a channel width direction of the plurality of memory cell transistors being in a skirt shape.

Abstract: A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Abstract: A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Abstract: In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.

Abstract: A semiconductor storage device has a plurality of word lines formed with a predetermined interval on a semiconductor substrate, a selection transistor provided at an end portion of the plurality of word lines, a first insulating film formed so as to cover side surfaces of the word lines, a side surface of the selection transistor, and a surface of the semiconductor substrate between the word lines, a high-permittivity film formed on the first insulation film, a second insulating film formed so as to cover the upper surface of the word lines and the selection transistor, a first air-gap portion located between the word lines and surrounded by the high-permittivity film and the second insulating film, and a second air-gap portion formed via the first insulating film and the high-permittivity film at a sidewall portion, which opposes the selection transistor, of the word line adjacent to the selection transistor, an upper portion of the second air-gap portion being covered by the second insulating film.

Abstract: A semiconductor storage device includes: a substrate having a semiconductor layer at least on a surface thereof; and a plurality of quantum dot elements forming a charge storage layer formed above the semiconductor layer via a first insulating film that becomes a tunnel insulating film in such a manner that the quantum dot elements are connected with a bit line in series, wherein each quantum dot element forms a single electron memory.

Abstract: A semiconductor device includes first and second memory cells lying adjacently each other, the first cell comprising first island region and first conductive spacer, the first region including first island semiconductor portion, first insulating film and first FG, the first spacer provided on upper side portion of first FG, the second cell comprising second island region and-second conductive spacer, the second region including second island semiconductor portion adjacent to the first portion, second insulating film and second FG, the second spacer provided on upper side portion of second FG, the cells comprising interelectrode insulating film (IPD) and the CG, edge of under portion of the IPD positioned lower than bottom surfaces of the FGs, edge of under portion of the CG positioned equal to the bottom surfaces of the FGs or lower, the IPD being failed to have bending portion between side surface of FGs and CG.

Abstract: A semiconductor device includes a pair of select gate structures which are opposed to each other and which are formed in a select transistor formation area, each of the select gate structures including a gate insulating film formed on a semiconductor substrate and a gate electrode formed on the gate insulating film, and a pair of memory cell gate structure groups which are formed in a pair of memory cell formation areas between which the select transistor formation area is interposed and each of which has a plurality of memory cell gate structures arranged at the same pitch, the pair of select gate structures having sides which are opposed to each other, and at least the upper portion of each of the opposed sides of the select gate structures being inclined.

Abstract: In a method for manufacturing a non-volatile semiconductor device according to this invention, steps are provided for forming a plurality of first semiconductor portions over a substrate; selectively growing a plurality of second semiconductor portions in contacting with said plurality of first semiconductor portions respectively; partially removing said plurality of second semiconductor portions to prepare a plurality of floating gates with substantially flat surfaces; forming an insulating layer over said plurality of floating gates; and forming a control gate over said insulating layer.

Abstract: Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.

Abstract: There are provided a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first metal wiring lines connecting to the first connection lines via first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second connection lines via second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, or with respect to resistivity of wiring materials, and a product of a wiring capacitance between adjacent two of the first metal wiring

Abstract: There are provided a plurality of first connection lines arranged in parallel with each other in a same layer, each connecting to a different contact portion; a plurality of second connection lines arranged in parallel with each other in the same layer as the first connection lines, the first connection lines and the second connection lines being arranged in an alternating fashion, and each of the second connection lines connecting to a different contact portion; a plurality of first metal wiring lines connecting to the first connection lines via first plugs; and a plurality of second metal wiring lines formed in a layer different from that of the first metal wiring lines, and connecting to the second connection lines via second plugs, the first metal wiring lines and the second metal wiring lines differing from each other with respect to at least one of thickness and width, or with respect to resistivity of wiring materials, and a product of a wiring capacitance between adjacent two of the first metal wiring

Abstract: Element isolation insulating layers have an STI structure, and their upper surfaces are flat. A floating gate electrode is formed in a recess which is formed by projections of the element isolation insulating layers. The two opposing side surfaces of the floating gate electrode are covered with the element isolation insulating layers. The upper surface of the floating gate electrode is substantially leveled with the upper surfaces of the element isolation insulating layers. A gate insulating layer is formed on the floating gate electrode and element isolation insulating layers. The underlayer of this gate insulating layer is flat. A control gate electrode is formed on the gate insulating layer.

Abstract: A semiconductor memory device has gate electrodes which are formed on a gate insulating film in direct contact therewith and have nitrogen-doped regions on their sides, or gate electrodes which use a nitrogen-doped polysilicon film. The widthwise end portions of the gate electrodes are located outward of the associated end portion of a semiconductor substrate under the gate electrodes and extend over device isolation regions. This structure can suppress a variation in the threshold voltages of memory cells when the semiconductor memory device operates. It is therefore possible to provide a highly reliable nonvolatile semiconductor memory device.