Patents by Inventor Hisataka Meguro

Hisataka Meguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of fabricating the same
    Publication number: 20010019152
    Abstract: Sidewall spacers comprised of a second polycrystalline silicon film are formed on the sides of a first polycrystalline silicon film in such a way that a relationship of b≦a=x<c/2 is satisfied where x is the thickness of the sidewall spacers, a is a distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film, b is the thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.
    Type: Application
    Filed: March 23, 2001
    Publication date: September 6, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hisataka Meguro
  • Method of making non-volatile memory with polysilicon spacers
    Patent number: 6235589
    Abstract: Sidewall spacers comprised of a second polycrystalline silicon film are formed on the sides of a first polycrystalline silicon film in such a way that a relationship of b≦a=x<c/2 is satisfied where x is the thickness of the sidewall spacers, a is a distance from the surface of the first insulating film to the surface of the first polycrystalline silicon film, b is the thickness of the second polycrystalline silicon film at a time of formation thereof and c is a distance between adjoining first polycrystalline silicon films.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: May 22, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hisataka Meguro
  • Semiconductor device having a nitrogen doped polysilicon layer
    Patent number: 5880498
    Abstract: A semiconductor device comprising, a semiconductor substrate, a first gate insulator film formed on the semiconductor substrate, a floating gate formed on the first gate insulator film, a second insulator film formed on the floating gate, a control gate formed on the second insulator film, and a silicon film doped with nitrogen and an impurity, and interposed between the floating gate and the second gate insulator film and/or between the second gate insulator film and the control gate.
    Type: Grant
    Filed: July 16, 1997
    Date of Patent: March 9, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Kinoshita, Hiroaki Tsunoda, Hisataka Meguro