Abstract: A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate, removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region, selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region, removing the second insulation film, polishing the second semiconductor layer in the third region using the second insulation film in the second region as a stopper after the second semiconductor layer is formed, and forming semiconductor elements on the first semiconductor layer and the second semiconductor layer after the second insulation film is removed.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Abstract: A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate, removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region, selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region, removing the second insulation film, polishing the second semiconductor layer in the third region using the second insulation film in the second region as a stopper after the second semiconductor layer is formed, and forming semiconductor elements on the first semiconductor layer and the second semiconductor layer after the second insulation film is removed.

Abstract: A semiconductor device includes a semiconductor substrate, an element-isolating region formed in the semiconductor substrate, a real element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof, and a dummy element region formed in the semiconductor substrate and outside the element-isolating region and having a metal silicide layer formed on the surface thereof. The ratio of the sum of pattern areas of the real element region and dummy element region occupied in a 1 ?m-square range of interest including the element region is 25% or more.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in substantially the same depth position as the undersurface of the buried oxide layer or in a position deeper than the buried oxide layer.

Abstract: A method for fabricating a semiconductor device, including forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate; removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region; selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region; and removing the second insulation film.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in a position deeper than the buried oxide layer.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: Disclosed is a semiconductor device and a process for producing a semiconductor device using a gate electrode such as an SRAM, wherein a gate electrode pattern is formed with fidelity to a reticle pattern through no complicated layout design and the gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.

Abstract: An SiO2 layer and an SiN layer are alternately stacked in regions 1 and 2 where the wiring film must be thin and thick, respectively, in such a manner that the stacked SiO2 and SiN layers constitute first through sixth interlayer insulating films. The SiN layer may be replaced with a layer of another material having an etching selection ratio with reference to SiO2. Then, resist having a cutout pattern is formed. The cutout pattern has a first via pattern in the first region and a first wiring pattern in the second region. With this resist used as a mask, the sixth, fifth, fourth and third insulating films are etched. Further, second resist having a cutout pattern is formed. The cutout pattern of the second resist has a second wiring pattern in the first region and a second via pattern in the second region. With the second resist used as a mask, the sixth and fifth insulating films are etched in the first region, and the second and first insulating films are etched in the second region.

Abstract: A semiconductor device, which is capable of improving isolation property of an isolation structure using STI without increasing impurity concentrations of wells, includes a well isolation structure in form of a shallow trench formed on the boundary between first and second wells opposite in conductivity type and adjacent to each other. When a first device region formed in the first well and a second device region formed in the second well are opposed at opposite sides of the well isolation structure, they are disposed at a first width (well isolation distance) than the second width when they are not opposed to each other. One of the device regions may be a dummy region which does not function as a circuit. In this configuration, angle of STI side walls is steeper, and STI width can be made smaller.

Abstract: A semiconductor device, comprises a first MOS transistor including a gate electrode having a gate width Le and a first gate post oxide film formed on the circumferential side wall of the gate electrode, and a second MOS transistor including a gate electrode having a gate width Li smaller than the gate width Le of the gate electrode of the first MOS transistor and a second gate post oxide film formed on a circumferential side wall of the gate electrode and having a portion differing in thickness from the first gate post oxide film.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: A semiconductor device, comprises a first MOS transistor including a gate electrode having a gate width Le and a first gate post oxide film formed on the circumferential side wall of the gate electrode, and a second MOS transistor including a gate electrode having a gate width Li smaller than the gate width Le of the gate electrode of the first MOS transistor and a second gate post oxide film formed on a circumferential side wall of the gate electrode and having a portion differing in thickness from the first gate post oxide film.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is formed in a first region of the semiconductor substrate. The second semiconductor layer is formed in a second region of the semiconductor substrate with an insulation film interposed between the semiconductor substrate and the second semiconductor layer. The third semiconductor layer is formed in a third region of a part of the semiconductor substrate with the insulation film and the second semiconductor layer extending in the third region and interposed between the semiconductor substrate and the third semiconductor layer. The top surface of the third semiconductor layer is higher than that of the second semiconductor layer in the second region.

Abstract: A semiconductor device, which is capable of improving isolation property of an isolation structure using STI without increasing impurity concentrations of wells, includes a well isolation structure in form of a shallow trench formed on the boundary between first and second wells opposite in conductivity type and adjacent to each other. When a first device region formed in the first well and a second device region formed in the second well are opposed at opposite sides of the well isolation structure, they are disposed at a first width (well isolation distance) than the second width when they are not opposed to each other. One of the device regions may be a dummy region which does not function as a circuit. In this configuration, angle of STI side walls is steeper, and STI width can be made smaller.

Abstract: A semiconductor device, comprises a first MOS transistor including a gate electrode having a gate width Le and a first gate post oxide film formed on the circumferential side wall of the gate electrode, and a second MOS transistor including a gate electrode having a gate width Li smaller than the gate width Le of the gate electrode of the first MOS transistor and a second gate post oxide film formed on a circumferential side wall of the gate electrode and having a portion differing in thickness from the first gate post oxide film.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is formed in a first region of the semiconductor substrate. The second semiconductor layer is formed in a second region of the semiconductor substrate with an insulation film interposed between the semiconductor substrate and the second semiconductor layer. The third semiconductor layer is formed in a third region of a part of the semiconductor substrate with the insulation film and the second semiconductor layer extending in the third region and interposed between the semiconductor substrate and the third semiconductor layer. The top surface of the third semiconductor layer is higher than that of the second semiconductor layer in the second region.