Abstract: Disclosed is a semiconductor device and a process for producing a semiconductor device using a gate electrode such as an SRAM, wherein a gate electrode pattern is formed with fidelity to a reticle pattern through no complicated layout design and the gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.

Abstract: Disclosed is a semiconductor device using a gate electrode such as an SRAM, wherein the electrode pattern is a formed with fidelity to a reticle pattern through no complicated layout design. The gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Abstract: An SiO2 layer and an SiN layer are alternately stacked in regions 1 and 2 where the wiring film must be thin and thick, respectively, in such a manner that the stacked SiO2 and SiN layers constitute first through sixth interlayer insulating films. The SiN layer may be replaced with a layer of another material having an etching selection ratio with reference to SiO2. Then, resist having a cutout pattern is formed. The cutout pattern has a first via pattern in the first region and a first wiring pattern in the second region. With this resist used as a mask, the sixth, fifth, fourth and third insulating films are etched. Further, second resist having a cutout pattern is formed. The cutout pattern of the second resist has a second wiring pattern in the first region and a second via pattern in the second region. With the second resist used as a mask, the sixth and fifth insulating films are etched in the first region, and the second and first insulating films are etched in the second region.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Abstract: An SiO2 layer and an SiN layer are alternately stacked in regions 1 and 2 where the wiring film must be thin and thick, respectively, in such a manner that the stacked SiO2 and SiN layers constitute first through sixth interlayer insulating films. The SiN layer may be replaced with a layer of another material having an etching selection ratio with reference to SiO2. Then, resist having a cutout pattern is formed. The cutout pattern has a first via pattern in the first region and a first wiring pattern in the second region. With this resist used as a mask, the sixth, fifth, fourth and third insulating films are etched. Further, second resist having a cutout pattern is formed. The cutout pattern of the second resist has a second wiring pattern in the first region and a second via pattern in the second region. With the second resist used as a mask, the sixth and fifth insulating films are etched in the first region, and the second and first insulating films are etched in the second region.

Abstract: A semiconductor device includes a first semiconductor layer formed above a first region of a supporting substrate with a buried oxide layer disposed therebetween and a second semiconductor layer formed on a second region of the supporting substrate. An interface between the supporting substrate and the second semiconductor layer is placed in substantially the same depth position as the undersurface of the buried oxide layer or in a position deeper than the buried oxide layer.

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer. The first semiconductor layer is formed in a first region of the semiconductor substrate. The second semiconductor layer is formed in a second region of the semiconductor substrate with an insulation film interposed between the semiconductor substrate and the second semiconductor layer. The third semiconductor layer is formed in a third region of a part of the semiconductor substrate with the insulation film and the second semiconductor layer extending in the third region and interposed between the semiconductor substrate and the third semiconductor layer. The top surface of the third semiconductor layer is higher than that of the second semiconductor layer in the second region.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same.

Abstract: A semiconductor device, comprises a first MOS transistor including a gate electrode having a gate width Le and a first gate post oxide film formed on the circumferential side wall of the gate electrode, and a second MOS transistor including a gate electrode having a gate width Li smaller than the gate width Le of the gate electrode of the first MOS transistor and a second gate post oxide film formed on a circumferential side wall of the gate electrode and having a portion differing in thickness from the first gate post oxide film.

Abstract: A method of manufacturing a semiconductor device substrate is disclosed, which comprises forming a mask layer patterned on a semiconductor layer insulated from a surface of a semiconductor substrate by an electrically insulating layer, etching the semiconductor layer according to the pattern of the mask layer to form a trench leading to the insulating layer, etching a protective layer deposited thinner on the semiconductor substrate than the thickness of the insulating layer to form a sidewall protective film which covers a side surface of the trench, etching the insulating layer from a bottom surface of the trench to the semiconductor substrate; and growing a single-crystalline layer from the surface of the semiconductor substrate exposed as a result of etching the insulating layer.

Abstract: A semiconductor chip comprises a base substrate, a bulk device region having a bulk growth layer on a part of the base substrate, an SOI device region having a buried insulator on the base substrate and a silicon layer on the buried insulator, and a boundary layer located at the boundary between the bulk device region and the SOI device region. The bulk device region has a first device-fabrication surface in which a bulk device is positioned on the bulk growth layer. The SOI device region has a second device-fabrication surface in which an SOI device is positioned on the silicon layer. The first and second device-fabrication surfaces are positioned at a substantially uniform level.

Abstract: The object of the present invention is to provide a semiconductor wafer in which a diffusion of Cu generated by a thermal treatment such as a Cu wiring formation step into silicon is prevented, and variations of transistor characteristics are lessened. The object of the present invention is to provide a method of manufacturing the same and a semiconductor device formed from the same. In the present invention, a protection insulating film for preventing Cu from diffusing into the inside of the wafer is formed on a peripheral portion of a principal plane, a external side plane and a rear plane of the wafer. With this protection insulating film, the diffusion of Cu that is a wiring material into a chip formation region of the wafer is prevented, so that the variations of the transistor characteristic.

Abstract: An SiO2 layer and an SiN layer are alternately stacked in regions 1 and 2 where the wiring film must be thin and thick, respectively, in such a manner that the stacked SiO2 and SiN layers constitute first through sixth interlayer insulating films. The SiN layer may be replaced with a layer of another material having an etching selection ratio with reference to SiO2. Then, resist having a cutout pattern is formed. The cutout pattern has a first via pattern in the first region and a first wiring pattern in the second region. With this resist used as a mask, the sixth, fifth, fourth and third insulating films are etched. Further, second resist having a cutout pattern is formed. The cutout pattern of the second resist has a second wiring pattern in the first region and a second via pattern in the second region. With the second resist used as a mask, the sixth and fifth insulating films are etched in the first region, and the second and first insulating films are etched in the second region.

Abstract: Disclosed is a semiconductor device and a process for producing a semiconductor device using a gate electrode such as an SRAM, wherein a gate electrode pattern is formed with fidelity to a reticle pattern through no complicated layout design and the gate electrode pattern is formed in an area smaller than that of a conventional semiconductor device. In a lithographic step using a reticle pattern provided with substantially linear gate electrode patterns, a projecting portion in which at least a part of a contact region is arranged is formed such that it is included in almost the center of a long side of a linear gate electrode pattern and a concave portion facing at least the entire length of the projecting portion is formed such that it is included in a long side opposite to the projecting portion between transistor regions of a reticle pattern.

Abstract: A semiconductor device, which is capable of improving isolation property of an isolation structure using STI without increasing impurity concentrations of wells, includes a well isolation structure in form of a shallow trench formed on the boundary between first and second wells opposite in conductivity type and adjacent to each other. When a first device region formed in the first well and a second device region formed in the second well are opposed at opposite sides of the well isolation structure, they are disposed at a first width (well isolation distance) than the second width when they are not opposed to each other. One of the device regions may be a dummy region which does not function as a circuit. In this configuration, angle of STI side walls is steeper, and STI width can be made smaller.

Abstract: A semiconductor device includes an n-channel MOSFET isolated by an element isolation region of STI structure. A silicon nitride (SiN) region is formed in an Si substrate near the interface between the element isolation region and the Si substrate. The silicon nitride region is formed by ion-implanting nitrogen (N) into the Si substrate. The silicon nitride region is acts as a barrier layer for preventing substrate impurity of the n-channel MOSFET (impurity contained in the channel region) from being thermally diffused into the element isolation region. The silicon nitride region is distributed from the main surface of the Si substrate in the end portion of the element isolation region to a region deeper than the substrate depth which determines the threshold voltage of the MOSFET.

Abstract: In a MISFET incorporating a silicide compound made of metal having a high melting point and formed on an impurity diffusion layer for the drain and source, a MISFET disclosed herein comprises an impurity diffusion layer for the drain and source, a gate insulating film, a gate electrode, a side-wall insulating film formed on the side wall of the gate electrode, an interlayer insulating film having an opened portion including a side-portion removed region obtained by removing a portion of the side portion of the side-wall insulating film on an impurity diffusion layer for the drain and source, a silicide compound layer formed on the impurity diffusion layer for the drain and source, the silicide compound layer being formed on the bottom surface of the opening of the interlayer insulating film corresponding to the side-portion removed region, and a conductor formed in the opening and made contact with the silicide compound layer.

Abstract: A gate electrode is formed in an element region of a semiconductor substrate. By ion implantation using the gate electrode as the mask, a low density doping (LDD) region is formed. By ion implantation after forming a side wall insulating film on the side wall of the gate electrode, source and drain regions are formed. Afterwards, by varying the thickness of the side wall insulating film of the side wall of the gate electrode, that is, by reducing the thickness of the side wall insulating film, a sufficient silicide region is formed on the source and drain regions. A silicide layer is formed on the gate electrode and source and drain regions by thermal reaction between a refractory metal and silicon in the gate electrode or in the semi-conductor substrate.

Abstract: A convex portion is formed along the edge of a semiconductor substrate to surround a chip region on the main surface side of the semiconductor substrate. For example, the convex portion is formed part of the semiconductor substrate. The height of the convex portion is set to approximately the same height as the surface of an insulating film attained after the end of the CMP (chemical mechanical polishing) process effected for the insulating film. The width the of the convex portion is set smaller than the width from the edge of the semiconductor substrate to a position in front of the chip region. The semiconductor substrate is attached to a carrier and the CMP process is effected by use of a polishing pad and a slurry. At the time of CMP, since a local heavy load occurring in the edge portion of the semiconductor substrate is applied only to the convex portion, the wafer edge over-polishing will not occur.