Patents by Inventor Hisayoshi Yamoto

Hisayoshi Yamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6500256
    Abstract: In case of epitaxially growing a single crystal silicon layer by catalytic CVD on a material layer in lattice alignment with single crystal silicon, i.e. a substrate of single crystal silicon, sapphire, spinel, or the like, the total pressure of the growth atmosphere is maintained in the range from 1.33×10−3 Pa to 4 Pa at least in the initial period of the epitaxial growth, or alternatively, partial pressure of oxygen and moisture in the growth atmosphere is maintained in the range from 6.65×10−10 to 2×10−6 Pa at least in the initial period of the epitaxial growth. Thus, the maximum oxygen concentration of the epitaxially grown single crystal silicon layer becomes not higher than 3×1018 atoms/cm−3 at least in a portion with the thickness of 10 nm from the boundary with the substrate 4. It is thus ensured to epitaxially grow a high-quality single crystal silicon layer at a lower temperature than that of existing CVD.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: December 31, 2002
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6492190
    Abstract: A single-crystal silicon layer is formed by graphoepitaxy from a low-melting-point metal layer which contains dissolved polycrystalline or amorphous silicon, or from a melt of a silicon-containing low-melting-point metal, using step differences formed on a substrate as a seed for the epitaxial growth. This single-crystal silicon layer is used as dual-gate MOSTFTS, or bottom-gate MOSTFTS, of an electrooptical device such as an LCD integrating a display section and a peripheral-driving-circuit section. This process enables production of a uniform single-crystal silicon thin-film having high electron/hole mobility at a relatively low temperature. The display section includes LDD-nMOSTFTs or pMOSTFTs having high switching characteristics and a low leakage current. The peripheral-driving-circuit section includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving ability.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: December 10, 2002
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi
  • Publication number: 20020160553
    Abstract: A method is disclosed for forming high-quality high-crystallinity polycrystalline or monocrystalline thin semiconductor film. The method is capable of forming such a semiconductor film over a large area at low cost. An apparatus for practicing the method is also disclosed. To form a high-crystallinity large-grain polycrystalline film or monocrystalline thin semiconductor film on a substrate, or to produce a semiconductor device including a high-crystallinity large-grain polycrystalline film or monocrystalline thin semiconductor film disposed on a substrate, a low-crystal-quality thin semiconductor film is first formed on the substrate, and then focused-light annealing is performed on the low-crystal-quality thin semiconductor film thereby melting or semi-melting the low-crystal-quality thin semiconductor film.
    Type: Application
    Filed: February 14, 2002
    Publication date: October 31, 2002
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto
  • Publication number: 20020104477
    Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.
    Type: Application
    Filed: August 29, 2001
    Publication date: August 8, 2002
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Publication number: 20020066901
    Abstract: Each of an electrooptical device and a driving substrate for the electrooptical device includes a first substrate having a display section provided with pixel electrodes and a peripheral-driving-circuit section provided on the periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate A gate section including a gate electrode and a gate-insulating film is formed on one surface of the first substrate, a compound layer having high lattice matching with single-crystal silicon is formed on the surface of the first substrate, and a single-crystal silicon layer is formed on the first substrate including the compound layer and the gate section. The single-crystal silicon layer constitutes a channel region, a source region, and a drain region.
    Type: Application
    Filed: October 10, 2001
    Publication date: June 6, 2002
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Sato, Hajime Yagi
  • Patent number: 6399429
    Abstract: Single-crystal silicon is deposited on an insulating substrate (1) with a crystalline sapphire layer (50) formed thereon as a seed, to form a silicon epitaxial layer (7). P-type impurity ions are implanted into a single-crystal silicon layer, and then N-type impurity ions are implanted to make a P-channel MOS transistor portion a single-crystal silicon layer (14). In a single-crystal silicon layer (11), an N+ source region (20) and drain region (21) of an N-channel MOS transistor are formed. Thus, a silicon layer is epitaxially grown uniformly at low temperatures.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: June 4, 2002
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka, Yuichi Satou, Hajime Yagi
  • Publication number: 20020056837
    Abstract: To form a monocrystalline silicon thin film having high electron/hole mobility uniformly at relatively low temperature, to permit manufacture of an electro-optic device such as a semiconductor device for a display using this monocrystalline silicon film, to permit manufacture of a nMOS or pMOSTFT display unit comprising an LDD having high switching performance and low leak current, and a peripheral circuit comprising a cMOS, n or pMOSTFT, or a combination thereof, of high drive performance, in a one-piece construction, thereby realizing a display panel having high image quality, fine detail, narrow frame edge, wide screen, high efficiency and large screen size wherein even a large glass substrate of relatively low strain point may be used, productivity is high, there is no need for costly equipment thereby permitting cost reductions, adjustment of threshold value is easy, and fast operation is possible due to reduction of resistance.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 16, 2002
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Satou, Hajime Yagi
  • Publication number: 20020047122
    Abstract: In case of growing a polycrystalline silicon layer (10) by catalytic CVD on a substrate (4) such as glass substrate, quartz substrate or silicon substrate having formed an oxide film on its surface, the total pressure of the growth atmosphere is maintained in the range from 1.33×10−3 Pa to 4 Pa at least in the initial period of the growth, or alternatively, partial pressure of oxygen and moisture in the grow that atmosphere is maintained in the range from 6.65×10−10 to 2×10−6 Pa at least in the initial period of the growth. Thus, the maximum oxygen concentration of the grown polycrystalline silicon layer (10) becomes not higher than 3×1018 atoms/cm−3 at least in a region of the polycrystalline silicon layer with the thickness of 10 nm from the boundary with the substrate (4). It is thus ensured to grow a high-quality polycrystalline silicon layer having a quality required for use as a TFT polycrystalline silicon layer by catalytic CVD.
    Type: Application
    Filed: December 8, 2000
    Publication date: April 25, 2002
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6376340
    Abstract: Polycrystalline silicon film forming methods to improve movement of electrons and holes and thus allow the fabrication of high performance semiconductor elements is needed. In a method of the present invention, polycrystalline is formed utilizing as a material, a chemical compound comprising at least one type of impurity from among tin (Sn), germanium (Ge) and lead (Pb) and a polycrystalline silicon film doped with impurities from at least one type from among tin (Sn), germanium (Ge) and lead (Pb) thus formed. In another method, polycrystalline silicon is formed, and the polycrystalline silicon film thus obtained is afterwards then doped with an impurity consisting of at least one type from among tin (Sn), germanium (Ge) and lead (Pb).
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: April 23, 2002
    Assignee: Sony Corporation
    Inventors: Yuuichi Sato, Hisayoshi Yamoto, Hideo Yamanaka, Hajime Yagi
  • Patent number: 6372558
    Abstract: The present invention provides an active matrix substrate having a built-in high-performance driver, in which a single crystal silicon thin film having high electron/hole mobility is uniformly deposited at a relatively low temperature, and an electrooptic device such as a thin film semiconductor device for display including the active matrix substrate. The single crystal silicon thin film is deposited by hetero epitaxial growth by a catalytic CVD method or the like using a crystalline sapphire thin film formed on the substrate as a seed so that the single crystal silicon layer obtained is used for top gate type MOSTFTs of the electrooptic device such as a LED or the like in which a display region and a peripheral driving circuit region are integrated.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: April 16, 2002
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Sato, Hajime Yagi
  • Patent number: 6355952
    Abstract: A capacitor in a ferroelectric nonvolatile memory (FERAM) comprising a lower electrode formed on a semiconductor substrate; a ferroelectric thin film formed on the lower electrode; an upper electrode formed on the ferroelectric thin film; a first protective layer consisting of one or more layers formed between the semiconductor substrate and the lower electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, silicon nitride, nickel and palladium; and a second protective layer consisting of one or more layers formed on the upper electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, nickel and palladium.
    Type: Grant
    Filed: September 27, 1996
    Date of Patent: March 12, 2002
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Akihiko Ochiai
  • Patent number: 6351010
    Abstract: Each of an electrooptical device and a driving substrate for the electrooptical device includes a first substrate having a display section provided with pixel electrodes and a peripheral-driving-circuit section provided on the periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate. A gate section including a gate electrode and a gate-insulating film is formed on one surface of the first substrate, a compound layer having high lattice matching with single-crystal silicon is formed on the surface of the first substrate, and a single-crystal silicon layer is formed on the first substrate including the compound layer and the gate section. The single-crystal silicon layer constitutes a channel region, a source region, and a drain region.
    Type: Grant
    Filed: September 16, 1999
    Date of Patent: February 26, 2002
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Sato, Hajime Yagi
  • Patent number: 6346718
    Abstract: An electro-optic device, such as an LCD, includes a display unit and a peripheral drive circuit unit on a single substrate. A gate comprising a gate electrode and gate insulation film is formed on a surface of the substrate. A layer of a substance having good lattice compatibility with monocrystalline silicon is formed over the gate insulation film. A layer of monocrystalline silicon is formed over the substance layer. Monocrystalline silicon is heteroepitaxially grown by catalytic CVD or the like using a crystalline sapphire film formed on the substrate to form the monocrystalline silicon layer. The monocrystalline silicon layer is used as a dual gate MOSTFT of the electro-optic device.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: February 12, 2002
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Satou, Hajime Yagi
  • Publication number: 20020013011
    Abstract: An electrooptical device including a first substrate including a display section having pixel electrodes and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate is produced as follows. A material layer having a high degree of lattice matching with single-crystal silicon is formed on one face of the first substrate. A polycrystalline or amorphous silicon layer is formed on the first substrate and then a low-melting-point metal layer is formed on or under the silicon layer on the first substrate, or a low-melting-point metal layer containing silicon is formed on the first substrate having the material layer. The silicon layer or the silicon is dissolved into the low-melting-point metal layer by a heat treatment.
    Type: Application
    Filed: March 2, 2001
    Publication date: January 31, 2002
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi
  • Publication number: 20020006681
    Abstract: A single-crystal silicon layer is formed by graphoepitaxy from a low-melting-point metal layer which contains dissolved polycrystalline or amorphous silicon, or from a melt of a silicon-containing low-melting-point metal, using step differences formed on a substrate as a seed for the epitaxial growth. This single-crystal silicon layer is used as dual-gate MOSTFTS, or bottom-gate MOSTFTS, of an electrooptical device such as an LCD integrating a display section and a peripheral-driving-circuit section. This process enables production of a uniform single-crystal silicon thin-film having high electron/hole mobility at a relatively low temperature. The display section includes LDD-nMOSTFTs or pMOSTFTs having high switching characteristics and a low leakage current. The peripheral-driving-circuit section includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving ability.
    Type: Application
    Filed: March 2, 2001
    Publication date: January 17, 2002
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi
  • Publication number: 20010036434
    Abstract: In case of epitaxially growing a single crystal silicon layer by catalytic CVD on a material layer in lattice alignment with single crystal silicon, i.e. a substrate of single crystal silicon, sapphire, spinel, or the like, the total pressure of the growth atmosphere is maintained in the range from 1.33×10−3 Pa to 4 Pa at least in the initial period of the epitaxial growth, or alternatively, partial pressure of oxygen and moisture in the growth atmosphere is maintained in the range from 6.65×10−10 to 2×10−6 Pa at least in the initial period of the epitaxial growth. Thus, the maximum oxygen concentration of the epitaxially grown single crystal silicon layer becomes not higher than 3×1018 atoms/cm−3 at least in a portion with the thickness of 10 nm from the boundary with the substrate 4. It is thus ensured to epitaxially grow a high-quality single crystal silicon layer at a lower temperature than that of existing CVD.
    Type: Application
    Filed: December 8, 2000
    Publication date: November 1, 2001
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6185031
    Abstract: The invention provides an optical switching method and apparatus by which the response time of a variation in refractive index of light can be further reduced. An electric field applied to a light passing element made of a substance containing conjugated system electrons is controlled to vary the condition of electrons of the substance of the light passing element to vary the refractive index of the light passing element. Then, the outgoing direction of light introduced into the light passing element is controlled to deflect the outgoing light from the light passing element, and the deflected outgoing light is introduced so as to be irradiated upon a selected control object element to control the control object element.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: February 6, 2001
    Assignee: Sony Corporation
    Inventors: Masataka Shingu, Hisayoshi Yamoto, Tohru Sugimoto
  • Patent number: 6103558
    Abstract: A single crystal silicon thin film having a high electron/hole mobility is uniformly formed at a relatively low temperature, so that production of an active matrix substrate having a built-in high performance driver and an electrooptical apparatus, such as a thin film semiconductor apparatus for display, becomes possible. A single crystal silicon layer is formed by hetero-epitaxial growth from a molten liquid layer of a low melting point metal having silicon dissolved therein by using a crystalline sapphire film formed on a substrate as a seed, and the single crystal silicon layer is used in a top gate type MOS TFT of an electrooptical apparatus, such as an LCD, in which a display part and a peripheral driving circuit are integrated.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: August 15, 2000
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Sato, Hajime Yagi
  • Patent number: 6090657
    Abstract: A capacitor in a ferroelectric nonvolatile memory (FERAM) comprising a lower electrode formed on a semiconductor substrate; a ferroelectric thin film formed on the lower electrode; an upper electrode formed on the ferroelectric thin film; a first protective layer consisting of one or more layers formed between the semiconductor substrate and the lower electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, silicon nitride, nickel and palladium; and a second protective layer consisting of one or more layers formed on the upper electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, nickel and palladium.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: July 18, 2000
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Akihiko Ochiai
  • Patent number: 5162892
    Abstract: A thin film semiconductor device with a polycrystalline silicon film forming an active channel region, a source region and a drain region, is encapsulated in a passivation layer which also serves as a source of free hydrogen. Migration of hydrogen into the active region improves the effective carrier mobility, the threshold voltage and the gate voltage of the device by reducing carrier trap density thereof. The passivation layer is activated during annealing to drive hydrogen through porous or transmissive layers of the device to the active region. Effective mobilities of up to 100 cm.sup.2 /V sec can be achieved in the preferred construction. The semicondcutor device can be fabricated in the form of IC chips.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: November 10, 1992
    Assignee: Sony Corporation
    Inventors: Hisao Hayashi, Hisayoshi Yamoto, Chiaki Sakai