Abstract: A semiconductor device includes: a plurality of memory cell arrays arranged along a predetermined direction; a plurality of bit lines to read data stored in a plurality of memory elements; a plurality of sense amplifier sections that amplify potentials appearing on selected bit lines, that amplify potentials in opposite phase to the potentials, and that output data signals and inverted data signals; a data output circuit that outputs the data to an external circuit based on the data signals and the inverted data signals; and a plurality of local signal lines extending parallel to the predetermined direction, to transmit the data signal and the inverted data signals to the data output circuit, wherein the local signal lines include two adjacent signal lines which are positionally switched around in a direction perpendicular to the predetermined direction alternately at predetermined intervals.

Abstract: To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.

Abstract: A semiconductor device includes a reduced-power-consumption circuit block which includes first and second power lines, and a first circuit cell. The first circuit cell includes a first functional-element-free region. The first functional-element-free region includes a first driver circuit configured to connect and disconnect the first power line and the second power line.

Abstract: A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated.

Abstract: A semiconductor device includes a first pad, and a sub-trunk line elongated in a first direction; a main-trunk line arranged between the first pad and the sub-trunk line and elongated in the first direction. The semiconductor device further includes a first plug line elongated in a second direction crossing the first direction, the first plug line being connected between the first pad and the main-trunk line without being direct contact with the sub-trunk line. The semiconductor device further includes a second plug line elongated in the second direction, the second plug line being connected between the main-trunk line and the sub-trunk line, and a first element coupled to the sub-trunk line.

Abstract: To include an input circuit block to which a plurality of bits are input and a processing circuit block that processes an internal signal output from the input circuit block. The input circuit block includes a plurality of unit input circuits arranged in an X direction to which the bits are input, respectively. Each of the unit input circuits includes an input wiring pattern that extends in a Y direction and a transistor of which a control electrode is connected to a corresponding one of the input wiring pattern. Coordinates of the input wiring pattern and the transistor corresponding to the input wiring pattern in the X direction do not overlap with each other. With this arrangement, by sharing the input wiring pattern between circuit blocks adjacent to each other in the Y direction, it is possible to reduce the number of pre-decode wirings.

Abstract: To include a plurality of circuit blocks each including a plurality of nonvolatile memory elements arranged in the X direction, a plurality of comparing circuits that are respectively allocated to the nonvolatile memory elements, and a determining circuit that is commonly allocated to the comparing circuits. The nonvolatile memory elements included in a predetermined circuit block among the circuit blocks are arranged in a first area. The comparing circuits and the determining circuit included in the predetermined circuit block are arranged side by side in the X direction in a second area that is located in the Y direction with respect to the first area. With this arrangement, because the circuit block becomes a shaped block, even when a plurality of circuit blocks are repeatedly arranged, it is possible to realize a further reduction of the chip area.

Abstract: A semiconductor device includes first and second wirings formed in a first wiring layer and extending parallel to an X direction, third and fourth wirings formed in a third wiring layer and extending parallel to a Y direction; fifth and sixth wirings formed in a second wiring layer positioned between the first and second wiring layers, a first contact conductor that connects the first wiring to the third wiring; and a second contact conductor that connects the second wiring to the fourth wiring. The first and second contact conductors are arranged in the X direction. According to the present invention, because the first and second contact conductors that connect wiring layers that are two or more layers apart are arranged in one direction, a prohibited area that is formed in the second wiring layer can be made narrower. Therefore, the flexibility of the layout of the second wiring layer is enhanced and the restriction on the wiring density can be relaxed.

Abstract: A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout. The parasitic parameter changing step includes a virtual wiring layer generation step of generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero, and a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer.

Abstract: A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated.

Abstract: A transistor of a characteristic checking element has a gate electrode connected to a measurement pad disposed in a dicing line and to an internal measurement pad disposed inside a semiconductor device. In a P/W process, a gate insulating film of the transistor is broken by an electric voltage applied via the internal measurement pad. Since the gate insulating film of the transistor is broken, a new current path is formed. Thus, measurement of accurate characteristics of the characteristic checking element is inhibited.

Abstract: A conductive pattern is provided in the vicinity of a bonding pad and connection is made therebetween using pillar-shaped leading interconnections. By providing an insulating film, in addition to the pillar-shaped leading interconnections, between the conductive pattern and the bonding pad, the impact at the time of bonding is weakened to thereby suppress offset of the conductive pattern. According to the pad structure of this invention, it becomes possible to reduce the pattern design standard around the bonding pad and thus a small-chip-size semiconductor integrated circuit is obtained.

Abstract: A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout. The parasitic parameter changing step includes a virtual wiring layer generation step of generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero, and a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer.

Abstract: A semiconductor memory device (100) has been disclosed. A semiconductor memory device (100) may include a select circuit region (31), a reading circuit region (33), and a memory cell array region (30). Memory cell array region (30) may include proximal memory cells (11A) and distal memory cells (11B) with respect to a select circuit region (31) or a reading circuit region (33). Distal memory cells (11B) have a current drive characteristic that may be greater than a current drive characteristic of proximal memory cells (11A). In this way, compensation may be provided and a data propagation delay difference due to parasitic values may be decreased.

Abstract: A semiconductor memory device (100) has been disclosed. A semiconductor memory device (100) may include a select circuit region (31), a reading circuit region (33), and a memory cell array region (30). Memory cell array region (30) may include proximal memory cells (11A) and distal memory cells (11B) with respect to a select circuit region (31) or a reading circuit region (33). Distal memory cells (11B) have a current drive characteristic that may be greater than a current drive characteristic of proximal memory cells (11A). In this way, compensation may be provided and a data propagation delay difference due to parasitic values may be decreased.

Abstract: Wood plates are dried by inserting the wood plates into respective spaces between a plurality of hot plates layered in steps. The wood plates are held, pressed and heat dried by and between the hot plates. A portion of spaces between the hot plates can be opened, and dried wood plates can be discharged from the opened spaces between the hot plates and undried wood plates can be inserted into such opened spaces. Those hot plates from which wood plates are not discharged or between which wood plates are not inserted are kept in a pressed state.

Abstract: A semiconductor memory device according to the present invention comprises a substantially rectangular memory cell array region formed on a surface of a semiconductor substrate, a bit line balancing circuit disposed adjacent to a predetermined side of the memory cell array region and having a first circuit layout pattern, a bit line potential supply circuit disposed outside the bit line balancing circuit remote from the memory cell array region and having a second circuit layout pattern and a first dummy wiring region disposed outside the bit line potential supply circuit remote from the memory cell array region and having a circuit layout pattern substantially the same as the first layout pattern. With this, reduction of mutual conductance of transistors constituting a peripheral circuit can be prevented and reduction of read/write rate of the semiconductor memory device and malfunction thereof are also prevented.

Abstract: A semiconductor integrated circuit employing a separate voltage supplying system in which a first circuit block is energized through a power supply line and a second circuit block is energized through another power supply line and provided with an improved protection circuit for the first circuit block is disclosed. The improved protection circuit includes a first discharge circuit for operatively discharging abnormal electrostatic charges at a signal line connected to the first circuit block to one power supply line and a second discharge circuit for operatively discharging abnormal electrostatic charges at the signal wiring to another power supply line.