Abstract: A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

Abstract: A semiconductor device includes a trench-gate IGBT enabling the fine adjustment of a gate capacitance independent from cell performance. In a gate wiring lead-out region, a plurality of trenches is arranged spaced apart from each other in an X direction perpendicular to a Y direction. Each trench has a shape enclosed by a rectangular outer outline and a rectangular inner outline in plan view. A trench gate electrode is provided in each of the trenches so as to be electrically coupled to an extraction electrode. To obtain an adequate breakdown voltage between a collector and an emitter, the trenches are formed in a p-type floating region. An n?-type drift region is formed in a region located inside an inner outline of the trench in plan view, whereby a capacitance formed between the trench gate electrode and the n?-type drift region is used as the reverse transfer capacitance.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface, a trench electrode placed inside a trench formed on the upper surface, and a trench insulating film placed between the trench electrode and the semiconductor substrate, and the semiconductor substrate includes a drift layer, a floating layer for electric field reduction, a hole barrier layer, a body layer and an emitter layer, and the emitter layer, the body layer and the hole barrier layer are separated from the drift layer by the floating layer for electric field reduction, and a path of a carrier passing through an inverted layer formed in the body layer includes the body layer, the hole barrier layer, a non-inverted region of the floating layer for electric field reduction, and the drift layer.

Abstract: The reliability of a semiconductor device is improved. A contact trench for coupling a field plate and a field limiting ring situated at the corner part of a semiconductor device is formed of a first straight line part and a second straight line part arranged line symmetrically with respect to the crystal orientation <011>. Respective one ends of the first straight line part and the second straight line part are coupled at the crystal orientation <011>, and the first straight line part and the second straight line part are set to extend in different directions from the crystal orientation <010> and the crystal orientation <011>.

Abstract: To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.

Abstract: A semiconductor device includes a power device and a temperature detection diode. The semiconductor device has a device structure configured to insulate between a power lien of the power device and the temperature detection diode.

Abstract: Respective outer peripheral surfaces (33, 35) of opening-side end portions (30, 31) of a front cover (12) and a pump shell (7), which have been shaped by pressing, are formed by slimming such that the outside diameters of the slimmed outer peripheral surfaces are equal to each other. With the opening-side end portions abutting against each other, a high-energy beam such as a laser beam (R) is radiated toward the abutment surfaces (30, 31) from the radially outer side to weld the abutment surfaces to each other. Consequently, it is possible to perform welding accurately through easy processing in order to easily manufacture a fluid coupling with high precision that facilitates post-processing.

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

Abstract: A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in a hybrid sub-cell region and an inactive cell region, and a contact trench penetrating it. Also, the contact trench is divided in a crossing region of extending directions of the hybrid sub-cell region and the emitter coupling section. Further, an n+-type emitter region is disposed so as to be apart from an end of the divided contact trench. With such configuration of not forming the contact trench in the crossing region, the working failure of the contact trench can be reduced. Also, because the n+-type emitter region is disposed so as to be apart from the end of the contact trench, the breakdown resistance of the semiconductor device can be improved.

Abstract: To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.