Abstract: A high-performance trench gate IGBT is provided. A trench gate IGBT according to one embodiment includes: a semiconductor substrate (11); a channel layer (15) provided on the semiconductor substrate (11); two floating P-type layer (12) provided on both sides of the channel layer 15, the floating P-type layers (12) being deeper than the channel layer (15); two emitter trenches (13) disposed between the two floating P-type layers (12), the emitter trenches (13) being respectively in contact with the floating P-type layers (12); at least two gate trenches (14) disposed between the two emitter trenches (13); and a source diffusion layer (19) disposed between the two gate trenches 14, the source diffusion layer (19) being in contact with each of the gate trenches (14).

Abstract: A coil component includes a magnetic body part and a coil part. The magnetic body part has first and second magnetic layers stacked together alternately in one axis direction, and cover parts covering the first and second magnetic layers from the one axis direction. The coil part has conductor patterns provided on the second magnetic layers. The magnetic body part includes: oblate soft magnetic grain-containing layers extending over the entire range of the magnetic body part in the direction perpendicular to the one axis direction, exposed in the direction perpendicular to the one axis direction, and formed by oblate soft magnetic grains whose thickness direction is oriented in the one axis direction; and spherical grain-containing layers adjoining the oblate soft magnetic grain-containing layers in the one axis direction, and formed by insulative spherical grains.

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.

Abstract: To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate.

Abstract: A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in a hybrid sub-cell region and an inactive cell region, and a contact trench penetrating it. Also, the contact trench is divided in a crossing region of extending directions of the hybrid sub-cell region and the emitter coupling section. Further, an n+-type emitter region is disposed so as to be apart from an end of the divided contact trench. With such configuration of not forming the contact trench in the crossing region, the working failure of the contact trench can be reduced. Also, because the n+-type emitter region is disposed so as to be apart from the end of the contact trench, the breakdown resistance of the semiconductor device can be improved.

Abstract: In an active region, a gate electrode is disposed in a trench. Spaced apart from the gate electrode, an emitter electrode is disposed in the trench. A source diffusion layer and a base diffusion layer are formed in the active region. The base diffusion layer has a base bottom portion inclined in such a manner that a portion of the base bottom portion adjacent to the emitter electrode is positionally deeper than a portion of the base bottom portion adjacent to the gate electrode. A contact portion has a contact bottom portion inclined in such a manner that a portion of the contact bottom portion in contact with the emitter electrode is positionally deeper than a portion of the contact bottom portion in contact with the base diffusion layer.

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.

Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

Abstract: To improve current detection performance of a sense IGBT particularly in a low current region in a semiconductor device equipped with a main IGBT and the sense IGBT used for current detection of the main IGBT. At a peripheral portion located at an outermost periphery of an active region surrounded by a dummy region within a sense IGBT cell, an n+-type semiconductor region is formed over an upper surface of a well of a floating state adjacent to a trench gate electrode embedded into a trench at an upper surface of a semiconductor substrate and applied with a gate voltage.

Abstract: A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in a hybrid sub-cell region and an inactive cell region, and a contact trench penetrating it. Also, the contact trench is divided in a crossing region of extending directions of the hybrid sub-cell region and the emitter coupling section. Further, an n+-type emitter region is disposed so as to be apart from an end of the divided contact trench. With such configuration of not forming the contact trench in the crossing region, the working failure of the contact trench can be reduced. Also, because the n+-type emitter region is disposed so as to be apart from the end of the contact trench, the breakdown resistance of the semiconductor device can be improved.

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.

Abstract: A semiconductor device including an IGBT element having features of a low on-state voltage and a low turn-off loss is provided. The semiconductor device is comprised of a trench gate type IGBT element. The IGBT element includes: a plurality of gate trench electrodes to which gate potential is given; and a plurality of emitter trench electrodes to which emitter potential is given. Between adjacent trench electrodes, a contact to an emitter electrode layer is formed. In this regard, there is formed, in the semiconductor substrate, a P type floating region which is in contact with bottom portions of at least some of the emitter trench electrodes via an interlayer insulation layer.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

Abstract: A linear active cell region is formed from a plurality of divided active cell regions arranged apart from each other in a second direction (y direction). The linear hole collector cell region is formed from a plurality of divided hole collector cell regions arranged apart from each other in the second direction (y direction). A P-type floating region is formed in a semiconductor substrate between the linear active cell region and the linear hole collector cell region adjacent to each other in a first direction (x direction), between the divided active cell regions adjacent to each other in the second direction (y direction), and between the divided hole collector cell regions adjacent to each other in the second direction (y direction).

Abstract: In characteristic test measurements of double-gate-in-trench p-channel power MOSFETs each having a p+ polysilicon gate electrode and a p+ field plate electrode in a trench, which were fabricated according to common design techniques, it has been found that, under conditions where a negative gate bias is applied continuously at high temperature with respect to the substrate, an absolute value of threshold voltage tends to increase steeply after the lapse of a certain period of stress application time. To solve this problem, the present invention provides a p-channel power MOSFET having an n-type polysilicon linear field plate electrode and an n-type polysilicon linear gate electrode in each trench part thereof.

Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

Abstract: The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N+-type emitter region of a linear active cell region via a contact groove formed on an interlayer insulating film and is coupled to a P-type body region of a linear hole connector cell region via a contact groove. The contact grooves arranged in the linear hole connector cell region are shorter than the contact groove in plan view.