Patents by Inventor Hitoshi Tsuji

Hitoshi Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040219865
    Abstract: The substrate polishing apparatus for polishing a polishing surface of a substrate comprises a film thickness monitoring device for monitoring a state of a film thickness of a thin film on the polishing surface of the substrate during polishing. The apparatus includes a table, a polishing member fixed on a surface of the table, a substrate support member for pressing the substrate onto the polishing member, an optical system composed of an optical fiber for irradiating the polishing surface of the substrate with a light of irradiation and an optical fiber for receiving a reflected light reflected on the polishing surface of the substrate, an analysis-processing system for processing an analysis of the reflected light received with the optical system, and the film-thickness monitoring device, wherein the table is provided with a liquid-feeding opening for feeding a translucent liquid into a through-hole disposed in the polishing member.
    Type: Application
    Filed: May 27, 2004
    Publication date: November 4, 2004
    Inventors: Yoichi Kobayashi, Shunsuke Nakai, Hitoshi Tsuji, Yasuo Tsukuda, Hiroki Yamauchi
  • Patent number: 6758723
    Abstract: The substrate polishing apparatus for polishing a polishing surface of a substrate comprises a film thickness monitoring device for monitoring a state of a film thickness of a thin film on the polishing surface of the substrate during polishing. The apparatus includes a table, a polishing member fixed on a surface of the table, a substrate support member for pressing the substrate onto the polishing member, an optical system composed of an optical fiber for irradiating the polishing surface of the substrate with a light of irradiation and an optical fiber for receiving a reflected light reflected on the polishing surface of the substrate, an analysis-processing system for processing an analysis of the reflected light received with the optical system, and the film-thickness monitoring device, wherein the table is provided with a liquid-feeding opening for feeding a translucent liquid into a through-hole disposed in the polishing member.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: July 6, 2004
    Assignees: Ebara Corporation, Shimadzu Corporation
    Inventors: Yoichi Kobayashi, Shunsuke Nakai, Hitoshi Tsuji, Yasuo Tsukuda, Hiroki Yamauchi
  • Publication number: 20030124957
    Abstract: The substrate polishing apparatus for polishing a polishing surface of a substrate comprises a film thickness monitoring device for monitoring a state of a film thickness of a thin film on the polishing surface of the substrate during polishing. The apparatus includes a table, a polishing member fixed on a surface of the table, a substrate support member for pressing the substrate onto the polishing member, an optical system composed of an optical fiber for irradiating the polishing surface of the substrate with a light of irradiation and an optical fiber for receiving a reflected light reflected on the polishing surface of the substrate, an analysis-processing system for processing an analysis of the reflected light received with the optical system, and the film-thickness monitoring device, wherein the table is provided with a liquid-feeding opening for feeding a translucent liquid into a through-hole disposed in the polishing member.
    Type: Application
    Filed: December 27, 2002
    Publication date: July 3, 2003
    Inventors: Yoichi Kobayashi, Shunsuke Nakai, Hitoshi Tsuji, Yasuo Tsukuda, Hiroki Yamauchi
  • Patent number: 6574081
    Abstract: A DC-DC converter has a primary-side circuit connected to a DC power supply and a converter for converting voltage supplied by the DC power supply into an AC signal; a secondary-side circuit for rectifying and smoothing the AC signal transmitted from the primary-side circuit to supply power to a load; and an auxiliary rectifying and smoothing circuit for rectifying and smoothing the AC signal transmitted from the primary-side circuit to supply sub-power supply voltage to the converter of the primary-side circuit. The primary-side circuit further has a monitoring circuit for monitoring the sub-power supply voltage supplied from the auxiliary rectifying and smoothing circuit to the converter and a stop circuit for latching a conversion operation of the converter into an OFF state.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: June 3, 2003
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tadahiko Matsumoto, Hitoshi Tsuji, Jun Nagai
  • Patent number: 6459594
    Abstract: A switching power supply apparatus has a transformer having a primary winding, a secondary winding and a tertiary winding; a primary switching element connected to the primary winding of the transformer for providing the primary winding with an input voltage in accordance with an on-off operation of the main switching element; an output circuit connected to the secondary winding of the transformer for receiving a voltage based on the input voltage from the secondary winding, rectifying the voltage and outputting an output voltage; a detection circuit in which the output voltage output from the output circuit is indirectly detected using the tertiary winding, and the detected voltage is output; a compensating-voltage-superposition circuit which generates a compensating voltage, in accordance with the detection voltage, for compensating a deviation of the detection voltage of the detection circuit to the output voltage of the output circuit in accordance with a change of the input voltage and which superposes t
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: October 1, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hitoshi Tsuji, Eito Moromizato
  • Patent number: 6414861
    Abstract: A DC-DC converter having a switching element and a synchronous rectifier, the switching element undergoing a switching operation, the converter performing a voltage conversion of an input voltage to provide a converted output voltage at an output/input conversion ratio that is determined by the switching operation of said switching element, the converter delivering the converted output voltage to a load, said DC-DC converter further comprising: a reverse current detector for detecting a reverse current which flows from an output of the converter to an input of the converter, and a reverse current suppressor, the reverse current suppressor controlling the switching operation of said switching element so as to increase the output/input conversion ratio when a reverse current is detected by the reverse current detector, thereby suppressing the reverse current.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: July 2, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tadahiko Matsumoto, Jun Nagai, Takayoshi Nishiyama, Hitoshi Tsuji
  • Patent number: 6314005
    Abstract: A DC-DC converter includes a primary side circuit for allowing a switching device to perform on/off operations to output energy in a primary coil of a transformer to a secondary coil. A secondary side circuit rectifies and smooths a voltage outputted from the secondary coil so as to output a DC-DC voltage. A voltage-detecting circuit rectifies and smooths a voltage outputted from a voltage-detecting coil provided in the transformer so as to output the voltage as a detected voltage corresponding to a voltage to be outputted from the secondary side circuit. A control circuit applies to the switching device a pulse control signal used for controlling on/off operation of the switching device according to the voltage outputted from the voltage-detecting circuit.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: November 6, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Koji Nishi, Koji Kitamura, Hitoshi Tsuji, Takayoshi Nishiyama, Yoshihiro Matsumoto, Tadahiko Matsumoto
  • Patent number: 6108894
    Abstract: A striker for use in a door latch apparatus comprises a base made of a normal-strength steel plate having a strength of 30 to 40 kg/mm.sup.2 and a U-shaped member made of a high-strength steel rod having a strength equal to or higher than 70 kg/mm.sup.2. The U-shaped member has inner and outer flanges, between which the base is firmly sandwiched. The inner flanges are formed without being heated. The U-shaped member is fixed to the base after hardened and tempered. After the U-shaped member is connected with the base, the base is not hardened or is not tempered.
    Type: Grant
    Filed: April 30, 1996
    Date of Patent: August 29, 2000
    Assignee: Mitsui Kinzoku Kogyo Kabushiki Kaisha
    Inventors: Tetsuro Mizuki, Hitoshi Tsuji, Koji Chikata
  • Patent number: 5958562
    Abstract: On a surface of an insulating board, a front wiring pattern is formed. On the rear surface of the insulating board, opposing the front wiring pattern, a rear wiring pattern is formed in a shape which is substantially plane-symmetrical to the front wiring pattern. An opening which penetrates the front wiring pattern and the rear wiring pattern is formed. At the inner wall of the opening, an electrically conductive layer is formed. Inside the opening, solder, for example, is placed to form an electrically conductive filling. As a result, the front wiring pattern and the rear wiring pattern are positively connected to each other electrically. Therefore, the current capacity and the heat capacity of the wiring patterns are increased, and the amount of generated heat is reduced.
    Type: Grant
    Filed: October 7, 1996
    Date of Patent: September 28, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hitoshi Tsuji, Koji Nishi
  • Patent number: 5933333
    Abstract: A switching power supply apparatus designed for suitably controlled stabilization of its output. The apparatus has a charge control circuit. If the voltage across an input capacitor is lower than a set voltage when a main power supply switching element turns on, a control circuit switching element turns on and energy is transferred from an input power source by conduction through the control circuit switching element and an inductance, and the inductance stores transferred energy. When the main switching element turns off, the charge control circuit turns off the control circuit switching element to supply the stored energy in the inductance to the input capacitor. If the voltage across the input capacitor is equal to or higher than the set voltage when the main switching element turns on, the control circuit switching element is maintained in the off state and the inductance cannot store energy. The voltage across the input capacitor is thereby limited.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: August 3, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Hitoshi Tsuji
  • Patent number: 5892665
    Abstract: An overcurrent protection circuit provided for a switching power supply has a current detector, voltage superposition device, and circuit for reducing a driving pulse. The current detector detects a circuit current in the switching power supply and converts it to a voltage. The voltage superposition device generates a constant voltage and superposes the voltage onto the detected voltage converted by the current detector. The detected voltage onto which the constant voltage has been superposed is applied between the base and the emitter of a transistor which functions as the circuit for reducing the driving pulse. If an overcurrent flows through the switching power supply, the transistor is turned on and a current flows into the transistor. As a result, a voltage applied to a maximum-duty-cycle setting terminal of a PWM IC provided for the switching power supply and used for pulse-width-modulation control of a switch device is reduced, and the overcurrent is suppressed.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: April 6, 1999
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Tadahiko Matsumoto, Seiichi Takahashi, Yoshihiro Matsumoto, Hitoshi Tsuji
  • Patent number: 5798203
    Abstract: In a method of making a negative photoresist image as for lithography, a positive resist is exposed by a light radiation through a phase shift mask as a first exposing step. Next, the positive resist is changed in its character by means of baking the substrate in an amine gas atmosphere such as ammonium, to make an exposed portion insoluble by developer. Next, an unexposed potion of the positive resist is exposed a second time to a light radiation using a second mask. After the second exposing step, the positive resist is developed to remove the unexposed portion. The phase shift mask has a fine pattern constituted mask membrane and an opening placed alternatively. And the opening is covered by attenuator intermittently. The second mask has an opening so that at least one portion unexposed by the first exposing step is exposed by the second exposing step.
    Type: Grant
    Filed: February 2, 1996
    Date of Patent: August 25, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Haraguchi, Hitoshi Tsuji
  • Patent number: 5707051
    Abstract: A wafer stage is provided with a plurality of through holes in its central and peripheral portions. To each of the through holes is coupled an end of a vacuum line the other end of which is coupled to a vacuum pump. With each of the vacuum lines is associated a respective one of electromagnetic valves. A controller controls the timing of opening of the electromagnetic valves. When a wafer placed on the stage is warped so that its central portion is higher than its peripheral portion, the electromagnetic valves associated with the vacuum lines coupled to the peripheral portion of the stage are opened first and the electromagnetic valves associated with the vacuum lines for the central portion of the stage are opened next.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: January 13, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Tsuji
  • Patent number: 5564682
    Abstract: A wafer stage is provided with a plurality of through holes in its central and peripheral portions. To each of the through holes is coupled an end of a vacuum line the other end of which is coupled to a vacuum pump. With each of the vacuum lines is associated a respective one of electromagnetic valves. A controller controls the timing of opening of the electromagnetic valves by sensing the direction of a warp in the wafer. When a wafer placed on the stage is warped so that its central portion is higher than its peripheral portion, the electromagnetic valves associated with the vacuum lines coupled to the peripheral portion of the stage are opened first and the electromagnetic valves associated with the vacuum lines for the central portion of the stage are opened next.
    Type: Grant
    Filed: August 8, 1994
    Date of Patent: October 15, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Tsuji
  • Patent number: 5514625
    Abstract: A novolak-based resist layer is formed on an interlayer insulating film, and that portion of the resist layer which is left as a resist mask for a wiring layer groove is formed by the first exposure and the heat treatment in an ammonia atmosphere. Thus, the solution rate of that portion of the resist layer is rendered low with regard to the alkali developing solution. Subsequently, the resist layer is exposed and developed in a regular manner to form a resist mask for defining a contact hole. With the obtained resist pattern used as a mask, the interlayer insulating film is etched to a depth which equals to a length of a contact hole in the depth direction formed at a later step. After that, with use of the resist pattern whose solution rate with respect to the alkali developing solution has been made low as a mask, the wiring layer groove is formed.
    Type: Grant
    Filed: March 15, 1995
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Tsuji
  • Patent number: 5432125
    Abstract: In a method of manufacturing a semiconductor apparatus, a resist is coated on a semiconductor substrate and baked. The resist is exposed with an electron beam, and an invertedly tapered opening is formed. Recess etching is performed on the semiconductor substrate through the opening. An electrode is formed at a location determined by the recess etching.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: July 11, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroto Misawa, Hitoshi Tsuji
  • Patent number: 5385851
    Abstract: In a method of manufacturing a semiconductor apparatus, a resist is coated on a semiconductor substrate and baked. The resist is exposed with an electron beam, and an invertedly tapered opening is formed. Recess etching is performed on the semiconductor substrate through the opening. An electrode is formed at a location determined by the recess etching.
    Type: Grant
    Filed: June 14, 1993
    Date of Patent: January 31, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroto Misawa, Hitoshi Tsuji
  • Patent number: 5320932
    Abstract: In a method of forming contact holes in an interstage insulation layer having a thick portion on the semiconductor substrate in which a first contact hole leading to the substrate surface is to be formed and a thin portion on an electrode in which a second contact hole leading to the electrode is to be formed, a positive-type resist layer is formed on the interstage insulation layer. Then first and second portions of the resist layer which are aligned with the first and second contact holes to be formed are exposed to light, and thereafter the resist layer is heated, thereby making the exposed first and second portions insoluble in a developer. Thereafter, the first portion of the resist layer is exposed to light and then subjected to a developing treatment to form an opening in the first portion of the resist layer.
    Type: Grant
    Filed: May 7, 1991
    Date of Patent: June 14, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Haraguchi, Hitoshi Tsuji, Yasuhisa Yoshida
  • Patent number: 5212117
    Abstract: A method of manufacturing a semiconductor device comprising the steps of forming a first insulating layer on a semiconductor substrate, forming a resist film sensitive to electron beams on the first insulating layer, applying electron beams onto a predetermined region of the resist film, removing unnecessary portions of the resist film by using a developer, thereby forming a remaining pattern resist film, forming a second insulating layer on the entire region of the first insulating layer and the remaining pattern resist film, simultaneously removing the remaining pattern resist film and the second insulating layer which is formed thereon, thereby forming an opening of a predetermined pattern on the second insulating layer, and etching the first insulating layer through the opening, using the second insulation layer as a mask, thereby causing a predetermined region of the semiconductor substrate to be exposed.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: May 18, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hitoshi Tsuji
  • Patent number: 5157003
    Abstract: Formation of an isolation region and an alignment mark different in depth in a semiconductor device is disclosed. Phenol resin positive resist has the property that when selective exposure process is implemented to such a resist to apply heat treatment thereto in an amine gas atmosphere such as ammonium, there results the state where only a photosensitive agent at the portion in which light reaction takes place is escaped or gotten away, so this resin portion is insoluble in an alkali developer. By making use of this property, when exposure process is implemented only to the region portions to be etched different in depth to carry out baking, only the position is established by a single mask. Thereafter, only the alignment mark portion required to be deeper of the regions to be etched is etched exposed to light to etch it thereafter to allow only the isolation region to be exposed to light to etch it. Thus, the alignment mark portion becomes deeper than the isolation region by two etching process steps.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: October 20, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Tsuji, Hiroshi Haraguchi