Patents by Inventor Hitoshi Tsuji

Hitoshi Tsuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5127989
    Abstract: The present invention provides a method of forming a thin film pattern with a trapezoidal cross section. In this method, a resist pattern with an inverted-trapezoidal cross section is formed on a thin film. Using the resist pattern with the inverted-trapezoidal cross section as a mask, the thin film is dry-etched. A resist pattern is left with the resist pattern used as a mask. The resist pattern has a trapezoidal cross section.
    Type: Grant
    Filed: May 13, 1991
    Date of Patent: July 7, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Haraguchi, Hitoshi Tsuji, Yasuto Otani, Kuniaki Kumamaru
  • Patent number: 4988609
    Abstract: In a patterning method according to this invention, a surface region of a resist layer is solution-retarded by a developer, and, then, the resist layer is patterned. Therefore, a desired shape of a side wall of the resist layer may be obtained by varying a solubility of the resist layer, with the result that a resist pattern with the side wall orthogonal to a surface of the substrate or the overhung side may be formed.
    Type: Grant
    Filed: June 13, 1988
    Date of Patent: January 29, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetsuna Hashimoto, Tiharu Kato, Hitoshi Tsuji
  • Patent number: 4985374
    Abstract: A manufacturing method of a semiconductor device of the present invention comprises a first step of exposing a periphery of a first region of a photoresist layer coating an insulating layer formed on a semiconductor substrate and a periphery of a second region for positioning, and a second step of heating said photoresist layer in ammonia atmosphere and forming an alkali insoluble portion in the periphery of the first region and that of the second region, a third step of exposing a third region, which is smaller than the first region, and the second region and developing these regions, a fourth step of etching the third region and the second region to a predetermined depth, and a fifth step of repeating the third and fourth steps once or more in a region, which is smaller than the third region, and the second region.
    Type: Grant
    Filed: June 27, 1990
    Date of Patent: January 15, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Tsuji, Hiroshi Haraguchi, Osamu Hirata, Hidetsuna Hashimoto
  • Patent number: 4792534
    Abstract: A method of manufacturing a semiconductor device having a submicron pattern. A p-type semiconductor layer is formed on an n-type semiconductor substrate. Insulating films are formed on the p-type semiconductor layer. A first mask layer, such as an aluminum layer having an etching rate different from that of the insulating films, is formed on the insulating films. A second mask layer having an etching rate different from that of the first mask layer, is formed on the first mask layer. The second mask layer is patterned. A coating film having an etching rate different from that of the first insulating film, is formed on the resultant structure. The coating film is etched to be left on a side wall of the patterned second mask layer. The first mask layer is patterned, using the residual coating film and the patterned second mask layer as masks, and a pattern finer than that of the resist is formed in the first mask layer.
    Type: Grant
    Filed: December 15, 1986
    Date of Patent: December 20, 1988
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Tsuji, Tiharu Kato, Kiyoshi Takaoki