Patents by Inventor Hitoshi Yamaguchi

Hitoshi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210322550
    Abstract: In one non-limiting embodiment, the present disclosure relates to lyophilized formulations containing an IL-31 antagonist (for example, an anti-IL-31RA antibody) as an active ingredient, the lyophilized formulations further containing arginine and/or a salt thereof and sucrose and/or trehalose. In another non-limiting embodiment, the present disclosure relates to solution formulations containing an IL-31 antagonist as an active ingredient, the solution formulations further containing arginine and/or a salt thereof.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 21, 2021
    Applicant: Chugai Seiyaku Kabushiki Kaisha
    Inventors: Daisuke Kameoka, Toru Yoshizawa, Megumi Numata, Hitoshi Sasaki, So Yamaguchi, Hiroko Murata, Naoka Hironiwa
  • Patent number: 11152244
    Abstract: An electrostatic chuck includes: a ceramic dielectric substrate; a base plate; and a heater plate. The heater plate includes a first and a second support plates including a metal, a heater element provided between the first and the second support plates, a first resin layer provided between the first support plate and the heater element, and a second resin layer provided between the second support plate and the heater element. A surface of the first support plate on the second support plate side includes a first region and a second region, the first region overlapping the heater element when viewed along the stacking direction, the second region not overlapping the heater element when viewed along the stacking direction. In a cross section parallel to the stacking direction, the second region protrudes toward the second support plate side compared to the first region.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: October 19, 2021
    Assignee: Toto Ltd.
    Inventors: Kosuke Yamaguchi, Hitoshi Sasaki, Kengo Maehata, Shumpei Kondo, Yuichi Yoshii
  • Publication number: 20210314278
    Abstract: [Problem] Efficiently utilizing physical resources in a communication system that builds a virtual network based on various requirements. [Solution] A communication system (10) includes a Spine switch group (12) consisting of a plurality of Spine switches (102), a Leaf switch group (14) consisting of a plurality of Leaf switches (104), a plurality of servers (106) connected to any one of the plurality of Leaf switches (104), and a controller (110) configured to build a virtual network on the physical resources. At least one of the Spine switch group (12) and the Leaf switch group (14) is constituted by a mix of switch devices having different performance. The controller (110) selects physical resources to be used for building the virtual network based on the desired performance of the virtual network.
    Type: Application
    Filed: August 7, 2019
    Publication date: October 7, 2021
    Inventors: Minoru YAMAGUCHI, Yoshinori KOIKE, Hitoshi IRINO, Hirotaka YOSHIOKA
  • Patent number: 10760687
    Abstract: To fulfill a sealing function for a fluid within a short period of time when a pump configured to pressure-feed the fluid is activated, provided are a seal ring, including: a first side surface (20); a second side surface (30) being a side surface on a side opposite to the first side surface (20); and a first side-surface side projecting portion (40) formed on the first side surface (20), in which a distal end portion (42) of the first side-surface side projecting portion (40) projects most toward an outward side from the first side surface (20) as compared to an entire surface of the first side surface (20) except for the distal end portion (42), and a sealing device using the same.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 1, 2020
    Assignee: TPR CO., LTD.
    Inventors: Hitoshi Yamaguchi, Teppei Oga
  • Patent number: 10451185
    Abstract: Provided is a seal ring causing less friction and having a low oil leakage property even under a state in which a shaft rotation frequency or a housing rotation frequency is high, and being capable of reducing a shaft rotation torque. A level difference portion that forms a second width smaller than a first width is formed on a longitudinal sectional shape of the seal ring as viewed in a circumferential direction from a seal ring outer peripheral surface side toward a seal ring inner peripheral surface side.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: October 22, 2019
    Assignee: TPR CO., LTD.
    Inventors: Hitoshi Yamaguchi, Teppei Oga
  • Patent number: 10406618
    Abstract: A cutting tap includes thread ridges, roots formed between the respective axially adjacent pairs of thread ridges, and a plurality of deburring thread grooves arranged at a constant pitch toward the axial front side of the cutting tap from the rearmost ones of the roots in which the deburring thread grooves are formed, and formed such that a groove bottom diameter of the deburring thread grooves gradually decreases toward the axial front side of the cutting tap. The respective deburring thread grooves have groove bottom diameter reliefs by which the groove bottom dimeter gradually decreases from the front side toward the rear side of each deburring thread groove in the rotation direction of the cutting tap, the groove bottom diameter reliefs being set to be larger than effective diameter reliefs of the thread grooves.
    Type: Grant
    Filed: March 24, 2015
    Date of Patent: September 10, 2019
    Assignee: SAKAI THREADING TOOL CO., LTD.
    Inventors: Yoshio Hachiuma, Hitoshi Yamaguchi
  • Publication number: 20190085981
    Abstract: To fulfill a sealing function for a fluid within a short period of time when a pump configured to pressure-feed the fluid is activated, provided are a seal ring, including: a first side surface (20); a second side surface (30) being a side surface on a side opposite to the first side surface (20); and a first side-surface side projecting portion (40) formed on the first side surface (20), in which a distal end portion (42) of the first side-surface side projecting portion (40) projects most toward an outward side from the first side surface (20) as compared to an entire surface of the first side surface (20) except for the distal end portion (42), and a sealing device using the same.
    Type: Application
    Filed: March 13, 2017
    Publication date: March 21, 2019
    Inventors: Hitoshi YAMAGUCHI, Teppei OGA
  • Publication number: 20190040956
    Abstract: Provided is a seal ring causing less friction and having a low oil leakage property even under a state in which a shaft rotation frequency or a housing rotation frequency is high, and being capable of reducing a shaft rotation torque. A level difference portion that forms a second width smaller than a first width is formed on a longitudinal sectional shape of the seal ring as viewed in a circumferential direction from a seal ring outer peripheral surface side toward a seal ring inner peripheral surface side.
    Type: Application
    Filed: October 21, 2016
    Publication date: February 7, 2019
    Inventors: Hitoshi YAMAGUCHI, Teppei OGA
  • Patent number: 10055683
    Abstract: A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: August 21, 2018
    Assignee: DENSO CORPORATION
    Inventor: Hitoshi Yamaguchi
  • Patent number: 9951429
    Abstract: A semiconductor photocatalyst includes first and second layers made of first and second materials, respectively. Band gaps of the first and second materials are equal to or smaller than 1.5 eV and 2.5 eV, respectively. A lower electric potential of a conduction band of the second material is disposed on a positive side from the first material. An upper electric potential of a valence band of the second material is disposed on a positive side from the first material and from an oxidation electric potential of water when the first and second layers are bonded to each other in the hetero junction manner. The lower electric potential of the conduction band of the first layer is disposed on a negative side from a reduction electric potential of hydrogen when the first and second layers are bonded to each other in the hetero junction manner.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: April 24, 2018
    Assignee: DENSO CORPORATION
    Inventor: Hitoshi Yamaguchi
  • Publication number: 20170189979
    Abstract: A cutting tap includes thread ridges, roots formed between the respective axially adjacent pairs of thread ridges, and a plurality of deburring thread grooves arranged at a constant pitch toward the axial front side of the cutting tap from the rearmost ones of the roots in which the deburring thread grooves are formed, and formed such that a groove bottom diameter of the deburring thread grooves gradually decreases toward the axial front side of the cutting tap. The respective deburring thread grooves have groove bottom diameter reliefs by which the groove bottom dimeter gradually decreases from the front side toward the rear side of each deburring thread groove in the rotation direction of the cutting tap, the groove bottom diameter reliefs being set to be larger than effective diameter reliefs of the thread grooves.
    Type: Application
    Filed: March 24, 2015
    Publication date: July 6, 2017
    Applicant: SAKAI THREADING TOOL CO., LTD.
    Inventors: Yoshio HACHIUMA, Hitoshi YAMAGUCHI
  • Patent number: 9515067
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: December 6, 2016
    Assignee: DENSO CORPORATION
    Inventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
  • Patent number: 9409472
    Abstract: Provided is an engine mount for a power unit. The power unit is supported by a support via the engine mount. The engine mount includes a first mounting bracket, a second mounting bracket, and a coating film. The coating film is applied to at least one of a surface of a first mounting portion and a surface of a second mounting portion. The coating film includes a cured-resin base layer made of a phenolic-resin adhesive, and an outer layer made of an epoxy-resin antirust paint and laminated on the cured-resin base layer. A thickness of the cured-resin base layer is 5 ?m or more. A thickness of the outer layer is less than 15 ?m. A sum total of the thickness of the cured-resin base layer and the thickness of the outer layer is equal to or more than 15 ?m and equal to or less than 30 ?m.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: August 9, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Keishi Hatanaka, Noriaki Yoshii, Yasuo Suzuki, Hitoshi Yamaguchi, Shinji Komura
  • Publication number: 20160032462
    Abstract: A semiconductor photocatalyst includes first and second layers made of first and second materials, respectively. Band gaps of the first and second materials are equal to or smaller than 1.5 eV and 2.5 eV, respectively. A lower electric potential of a conduction band of the second material is disposed on a positive side from the first material. An upper electric potential of a valence band of the second material is disposed on a positive side from the first material and from an oxidation electric potential of water when the first and second layers are bonded to each other in the hetero junction manner. The lower electric potential of the conduction band of the first layer is disposed on a negative side from a reduction electric potential of hydrogen when the first and second layers are bonded to each other in the hetero junction manner.
    Type: Application
    Filed: June 24, 2015
    Publication date: February 4, 2016
    Inventor: Hitoshi YAMAGUCHI
  • Publication number: 20150352939
    Abstract: Provided is an engine mount for a power unit. The power unit is supported by a support via the engine mount. The engine mount includes a first mounting bracket, a second mounting bracket, and a coating film. The coating film is applied to at least one of a surface of a first mounting portion and a surface of a second mounting portion. The coating film includes a cured-resin base layer made of a phenolic-resin adhesive, and an outer layer made of an epoxy-resin antirust paint and laminated on the cured-resin base layer. A thickness of the cured-resin base layer is 5 ?m or more. A thickness of the outer layer is less than 15 ?m. A sum total of the thickness of the cured-resin base layer and the thickness of the outer layer is equal to or more than 15 ?m and equal to or less than 30 ?m.
    Type: Application
    Filed: May 21, 2015
    Publication date: December 10, 2015
    Inventors: Keishi HATANAKA, Noriaki YOSHII, Yasuo SUZUKI, Hitoshi YAMAGUCHI, Shinji KOMURA
  • Patent number: 9187343
    Abstract: Means for reducing an arsenic ion concentration in the solution to the degree of ultra trace amount are provided. Ammonium molybdate is supported by a nanostructure material by mixing the nanostructure material, which is obtained after the nanostructure material such as an alumina reacts with a surfactant, in the solution containing the ammonium molybdate. The nanostructure material supporting an arsenic ion adsorption compound such as ammonium molybdate can selectively adsorb and remove trace of arsenic ion in the solution by a room temperature treatment without a water conditioning such as pH control. In our removal system of arsenic, extra posttreatments are not needed because special pretreatments are not carried out, and special heating equipments are not used. Accordingly, our removal system of arsenic can be constructed at low cost. Furthermore, it can supply an arsenic-free solution by be constructed at multi stages.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: November 17, 2015
    Assignee: National Institute for Materials Science
    Inventors: Sherif El-Safty, Ahmed Shahat Ahmed, Kohmei Halada, Mohamed Shenashen, Ahmed Abouelmagd, Hitoshi Yamaguchi
  • Publication number: 20150100532
    Abstract: A plurality of synapse determination circuits are provided on a one-to-one basis for a plurality of gate electrodes of a multi-input gate electrode in a neuron element. With respect to first image regions where “1” is repeatedly inputted in correspondence with group information, the synapse determination circuits corresponding to the first image regions are excitatory synapses. With respect to second image regions where “0” is repeatedly inputted in correspondence with the group information, the synapse determination circuits corresponding to the second image regions are inhibitory synapses.
    Type: Application
    Filed: August 11, 2014
    Publication date: April 9, 2015
    Inventor: Hitoshi YAMAGUCHI
  • Publication number: 20150041850
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Application
    Filed: October 14, 2014
    Publication date: February 12, 2015
    Inventors: Hirotaka SAIKAKU, Tsuyoshi YAMAMOTO, Shoji MIZUNO, Masakiyo SUMITOMO, Tetsuo FUJII, Jun SAKAKIBARA, Hitoshi YAMAGUCHI, Yoshiyuki HATTORI, Rie TAGUCHI, Makoto KUWAHARA
  • Patent number: 8890252
    Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 18, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
  • Publication number: 20140001125
    Abstract: Means for reducing an arsenic ion concentration in the solution to the degree of ultra trace amount are provided. Ammonium molybdate is supported by a nanostructure material by mixing the nanostructure material, which is obtained after the nanostructure material such as an alumina reacts with a surfactant, in the solution containing the ammonium molybdate. The nanostructure material supporting an arsenic ion adsorption compound such as ammonium molybdate can selectively adsorb and remove trace of arsenic ion in the solution by a room temperature treatment without a water conditioning such as pH control. In our removal system of arsenic, extra posttreatments are not needed because special pretreatments are not carried out, and special heating equipments are not used. Accordingly, our removal system of arsenic can be constructed at low cost. Furthermore, it can supply an arsenic-free solution by be constructed at multi stages.
    Type: Application
    Filed: January 12, 2012
    Publication date: January 2, 2014
    Applicant: NATIONAL INSTITUTE FOR MATERIALS SCIENCE
    Inventors: Sherif El-Safty, Ahmed Shahat Ahmed, Kohmei Halada, Mohamed Shenashen, Ahmed Abouelmaged, Hitoshi Yamaguchi