Patents by Inventor Hitoshi Yamaguchi
Hitoshi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8593134Abstract: A current sensor includes first to fourth magneto-resistive elements each having a resistance value; and a compensation current line applying a compensation magnetic field to the magneto-resistive elements. A bridge circuit is formed by the magneto-resistive elements. Resistance values of the first and third magneto-resistive elements change together in one increasing/decreasing direction. Resistance values of the second and fourth magneto-resistive elements change together in the other increasing/decreasing direction. The compensation current is generated by a potential difference between the first and second junctions in response to application of voltage between the third and fourth junctions. The compensation current line includes first to fourth line portions. Each line portion extends in the same direction as the extending direction of the magneto-resistive elements, overlaps the corresponding magneto-resistive elements, and. The current-to-be-detected is detected based on the compensation current.Type: GrantFiled: March 8, 2011Date of Patent: November 26, 2013Assignee: TDK CorporationInventors: Susumu Haratani, Hitoshi Yamaguchi, Masahiro Miyazaki, Shigeru Shimura
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Patent number: 8384153Abstract: A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.Type: GrantFiled: July 7, 2011Date of Patent: February 26, 2013Assignee: DENSO CORPORATIONInventors: Tsuyoshi Yamamoto, Masakiyo Sumitomo, Hitoshi Yamaguchi, Nozomu Akagi, Yuma Kagata
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Patent number: 8351185Abstract: The invention provides an electronic component and a manufacturing method thereof that can achieve an improved adhesion strength when the electronic component is solder-mounted onto an external substrate and can thereby obtain considerably improved electric properties and reliabilities, etc. An electronic component, which is a capacitor 1, has: a circuit element 5a formed on a substrate 2; an electrode layer 5b connected to the circuit element 5a; passivation layers 6 and 8 that cover the electrode layer 5b; and terminal electrodes 9a and 9b connected to the electrode layer 5b via via-conductors Va and Vb formed through the passivation layers 6 and 8, the terminal electrodes 9a and 9b being formed to cover the side wall of the passivation layers 6 and 8.Type: GrantFiled: August 10, 2010Date of Patent: January 8, 2013Assignee: TDK CorporationInventors: Takashi Ohtsuka, Kyung-Ku Choi, Tatsuo Namikawa, Hitoshi Yamaguchi
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Patent number: 8326222Abstract: A signal transmission device includes: an input signal conductor in which an input signal current flows and thereby generating an input signal magnetic field; a magnetically-biasing conductor in which a biasing current flows and thereby generating a biasing magnetic field; and one or more magnetoresistive elements in each of which a sensing current flows and thereby generating a self-biasing magnetic field, and each including a magnetization free layer having a magnetization direction which varies in response to the input signal magnetic field, the biasing magnetic field, and the self-biasing magnetic field. Each of the biasing magnetic field and the self-biasing magnetic field is applied to the magnetization free layer in a same direction to each other.Type: GrantFiled: March 22, 2010Date of Patent: December 4, 2012Assignee: TDK CorporationInventors: Susumu Haratani, Hitoshi Yamaguchi, Masahiro Miyazaki, Yoshio Sase, Shigeru Shimura
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Patent number: 8324509Abstract: The invention provides an electronic component and a manufacturing method thereof that: can allow electronic components to be mounted on an external substrate at a higher density than before; can adjust the height (level) of a terminal electrode as required and desired, thereby solving problems that would occur in the inspection of the conventional electronic components; and can also improve the yield in the mounting of electronic components, thereby achieving increased productivity.Type: GrantFiled: August 10, 2010Date of Patent: December 4, 2012Assignee: TDK CorporationInventors: Takashi Ohtsuka, Kyung-Ku Choi, Tatsuo Namikawa, Hitoshi Yamaguchi
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Patent number: 8215881Abstract: A rotary cutting tool is provided which is less likely to cause chips to get stuck, and which can be manufactured at a low cost. The rotary cutting tool includes a body having a relief surface (6) and a rake face (7) which is connected to the relief surface (6). An oxide film (9) is formed on the rake face (7) by oxidizing the surface of the body, and a hard film (8) is formed on the relief surface (6) and the oxide film (9), The hard film (8) is made of a metal carbide, a metal nitride, a metal carbonitride, or a solid solution thereof.Type: GrantFiled: January 15, 2007Date of Patent: July 10, 2012Assignee: Sakai Threading Tool Co., Ltd.Inventor: Hitoshi Yamaguchi
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Publication number: 20120025874Abstract: A semiconductor device includes a switching element having: a drift layer; a base region; an element-side first impurity region in the base region; an element-side gate electrode sandwiched between the first impurity region and the drift layer; a second impurity region contacting the drift layer; an element-side first electrode coupled with the element-side first impurity region and the base region; and an element-side second electrode coupled with the second impurity region, and a FWD having: a first conductive layer; a second conductive layer; a diode-side first electrode coupled to the second conductive layer; a diode-side second electrode coupled to the first conductive layer; a diode-side first impurity region in the second conductive layer; and a diode-side gate electrode in the second conductive layer sandwiched between first impurity region and the first conductive layer and having a first gate electrode as an excess carrier injection suppression gate.Type: ApplicationFiled: July 26, 2011Publication date: February 2, 2012Applicant: DENSO CORPORATIONInventors: Hirotaka Saikaku, Tsuyoshi Yamamoto, Shoji Mizuno, Masakiyo Sumitomo, Tetsuo Fujii, Jun Sakakibara, Hitoshi Yamaguchi, Yoshiyuki Hattori, Rie Taguchi, Makoto Kuwahara
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Publication number: 20120007173Abstract: A semiconductor device includes: a substrate; multiple first and second conductive type regions on the substrate for providing a super junction structure; a channel layer on the super junction structure; a first conductive type layer in the channel layer; a contact second conductive type region in the channel layer; a gate electrode on the channel layer via a gate insulation film; a surface electrode on the channel layer; a backside electrode on the substrate opposite to the super junction structure; and an embedded second conductive type region. The embedded second conductive type region is disposed in a corresponding second conductive type region, protrudes into the channel layer, and contacts the contact second conductive type region. The embedded second conductive type region has an impurity concentration higher than the channel layer, and has a maximum impurity concentration at a position in the corresponding second conductive type region.Type: ApplicationFiled: July 7, 2011Publication date: January 12, 2012Applicant: DENSO CORPORATIONInventors: Tsuyoshi YAMAMOTO, Masakiyo SUMITOMO, Hitoshi YAMAGUCHI, Nozomu AKAGI, Yuma KAGATA
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Publication number: 20110227560Abstract: A current sensor includes first to fourth magneto-resistive elements each having a resistance value; and a compensation current line applying a compensation magnetic field to the magneto-resistive elements. A bridge circuit is formed by the magneto-resistive elements. Resistance values of the first and third magneto-resistive elements change together in one increasing/decreasing direction. Resistance values of the second and fourth magneto-resistive elements change together in the other increasing/decreasing direction. The compensation current is generated by a potential difference between the first and second junctions in response to application of voltage between the third and fourth junctions. The compensation current line includes first to fourth line portions. Each line portion extends in the same direction as the extending direction of the magneto-resistive elements, overlaps the corresponding magneto-resistive elements, and. The current-to-be-detected is detected based on the compensation current.Type: ApplicationFiled: March 8, 2011Publication date: September 22, 2011Applicant: TDK CORPORATIONInventors: Susumu HARATANI, Hitoshi YAMAGUCHI, Masahiro MIYAZAKI, Shigeru SHIMURA
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Patent number: 7968953Abstract: A semiconductor device includes a substrate, a plurality of first columns having a first conductivity type, a plurality of second columns having a second conductivity type, a first electrode, and a second electrode. The first columns and the second columns are alternately arranged on the substrate to provide a super junction structure. The first electrode is disposed on the super junction structure, forms schottky junctions with the first columns, and forms ohmic junctions with the second columns. The second electrode is disposed on the substrate on an opposite side of the super junction structure. At least a part of the substrate and the super junction structure has lattice defects to provide a lifetime control region at which a lifetime of a minority carrier is controlled to be short.Type: GrantFiled: March 31, 2008Date of Patent: June 28, 2011Assignee: DENSO CORPORATIONInventors: Jun Sakakibara, Hitoshi Yamaguchi
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Patent number: 7956609Abstract: The magnetic sensor comprises a spin-valve GMR including a free layer having an elongated form as seen in a laminating direction and a permanent magnet layer having an elongated form as seen in the laminating direction. The permanent magnet layer is arranged in parallel with the free layer.Type: GrantFiled: March 21, 2008Date of Patent: June 7, 2011Assignee: TDK CorporationInventors: Susumu Haratani, Hitoshi Yamaguchi, Naoki Ohta
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Patent number: 7948349Abstract: A magnetic coupler having higher response is provided. The magnetic coupler includes a thin film coil wound in a first layer; a first MR element being disposed in a second layer, and detecting an induced magnetic field generated by a signal current flowing through the thin film coil; and yokes being disposed close to the first MR element, and including a soft magnetic material. The first MR element is disposed in a position corresponding to a linear region of the thin film coil in a stacking direction. The yokes are disposed at both of an inner turn side and an outer turn side of the thin film coil in a manner of interposing the first MR element in the second layer. Thus, reduction in intensity of the induced magnetic field is suppressed, and intensity distribution of the induced magnetic field becomes flatter.Type: GrantFiled: October 27, 2008Date of Patent: May 24, 2011Assignee: TDK CorporationInventors: Susumu Haratani, Hitoshi Yamaguchi
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Patent number: 7932553Abstract: A semiconductor device includes an insulated gate transistor and a resistor. The insulated gate transistor includes a plurality of first cells for supplying electric current to a load and a second cell for detecting an electric current that flows in the first cells. A gate terminal of the plurality of first cells is coupled with a gate terminal of the second cell and a source terminal of the plurality of first cells is coupled with a source terminal of the second cell on a lower potential side. The resistor has a first terminal coupled with a drain terminal of the second cell and a second terminal coupled with a drain terminal of the first cells on a higher potential side. A gate voltage of the insulated gate transistor is feedback-controlled based on an electric potential of the resistor.Type: GrantFiled: November 18, 2008Date of Patent: April 26, 2011Assignee: Denso CorporationInventors: Hitoshi Yamaguchi, Tsuyoshi Yamamoto
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Patent number: 7928470Abstract: A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.Type: GrantFiled: November 14, 2006Date of Patent: April 19, 2011Assignee: DENSO CORPORATIONInventors: Hitoshi Yamaguchi, Jun Sakakibara
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Patent number: 7911023Abstract: A semiconductor apparatus is disclosed. The semiconductor apparatus includes a semiconductor substrate that has a first surface and a second surface opposite to each other. The semiconductor apparatus further includes multiple double-sided electrode elements each having a pair of electrodes located respectively on the first and second surfaces of the semiconductor substrate. A current flows between the first and second electrode. Each double-sided electrode element has a PN column region located in the semiconductor substrate. The semiconductor apparatus further includes an insulation trench that surrounds each of multiple double-sided electrode elements, and that insulates and separates the multiple double-sided electrode elements from each other.Type: GrantFiled: November 4, 2008Date of Patent: March 22, 2011Assignee: Denso CorporationInventors: Nozomu Akagi, Hitoshi Yamaguchi, Tetsuo Fujii
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Publication number: 20110044011Abstract: The invention provides an electronic component and a manufacturing method thereof that can achieve an improved adhesion strength when the electronic component is solder-mounted onto an external substrate and can thereby obtain considerably improved electric properties and reliabilities, etc. An electronic component, which is a capacitor 1, has: a circuit element 5a formed on a substrate 2; an electrode layer 5b connected to the circuit element 5a; passivation layers 6 and 8 that cover the electrode layer 5b; and terminal electrodes 9a and 9b connected to the electrode layer 5b via via-conductors Va and Vb formed through the passivation layers 6 and 8, the terminal electrodes 9a and 9b being formed to cover the side wall of the passivation layers 6 and 8.Type: ApplicationFiled: August 10, 2010Publication date: February 24, 2011Applicant: TDK CORPORATIONInventors: Takashi OHTSUKA, Kyung-Ku Choi, Tatsuo Namikawa, Hitoshi Yamaguchi
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Publication number: 20110042127Abstract: The invention provides an electronic component and a manufacturing method thereof that: can allow electronic components to be mounted on an external substrate at a higher density than before; can adjust the height (level) of a terminal electrode as required and desired, thereby solving problems that would occur in the inspection of the conventional electronic components; and can also improve the yield in the mounting of electronic components, thereby achieving increased productivity.Type: ApplicationFiled: August 10, 2010Publication date: February 24, 2011Applicant: TDK CORPORATIONInventors: Takashi OHTSUKA, Kyung-Ku Choi, Tatsuo Namikawa, Hitoshi Yamaguchi
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Patent number: 7858475Abstract: A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.Type: GrantFiled: November 9, 2009Date of Patent: December 28, 2010Assignee: DENSO CORPORATIONInventors: Hitoshi Yamaguchi, Takeshi Miyajima, Nozomu Akagi
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Patent number: 7859048Abstract: A semiconductor device includes: a first semiconductor layer; a PN column layer having first and second column layers; and a second semiconductor layer. Each of the first and second column layers includes first and second columns alternately arranged along with a horizontal direction. The first and second column layers respectively have first and second impurity amount differences defined at a predetermined depth by subtracting an impurity amount in the second column from an impurity amount in the first column. The first impurity amount difference is constant and positive. The second impurity amount difference is constant and negative.Type: GrantFiled: December 16, 2008Date of Patent: December 28, 2010Assignee: Denso CorporationInventors: Yuma Kagata, Jun Sakakibara, Hitoshi Yamaguchi
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Patent number: RE44236Abstract: A method for manufacturing a semiconductor device includes the steps of: forming a trench in a semiconductor substrate; and forming an epitaxial film on the substrate including a sidewall and a bottom of the trench so that the epitaxial film is filled in the trench. The step of forming the epitaxial film includes a final step before the trench is filled with the epitaxial film. The final step has a forming condition of the epitaxial film in such a manner that the epitaxial film to be formed on the sidewall of the trench has a growth rate at an opening of the trench smaller than a growth rate at a position of the trench, which is deeper than the opening of the trench.Type: GrantFiled: October 12, 2011Date of Patent: May 21, 2013Assignees: DENSO CORPORATION, Sumco CorporationInventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Tomoatsu Makino, Syouji Nogami, Tomonori Yamaoka