Patents by Inventor Hitoshi Yamaguchi

Hitoshi Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7364971
    Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: April 29, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Mikimasa Suzuki, Yoshiyuki Hattori
  • Patent number: 7364980
    Abstract: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Y?m/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: April 29, 2008
    Assignees: Sumco Corporation, Denso Corporation
    Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Hitoshi Yamaguchi, Takumi Shibata
  • Patent number: 7345339
    Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: March 18, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Mikimasa Suzuki, Yoshiyuki Hattori
  • Publication number: 20080038850
    Abstract: A manufacturing method of a semiconductor device includes: forming multiple trenches on a semiconductor substrate; forming a second conductive type semiconductor film in each trench to provide a first column with the substrate between two trenches and a second column with the second conductive type semiconductor film in the trench, the first and second columns alternately repeated along with a predetermined direction; thinning a second side of the substrate; and increasing an impurity concentration in a thinned second side so that a first conductive type layer is provided. The impurity concentration of the first conductive type layer is higher than the first column. The first column provides a drift layer so that a vertical type first-conductive-type channel transistor is formed.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Applicant: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Takeshi Miyajima
  • Patent number: 7317213
    Abstract: A semiconductor device includes: a center region; a periphery region; and a semiconductor layer including pairs of a first region having a first impurity amount and a second region having a second impurity amount. The first and the second regions are alternately aligned in a plane. The periphery region includes an utmost outer and an utmost inner periphery pairs. The utmost outer periphery pair has a difference between the second and the first impurity amounts, which is smaller than a maximum difference in the periphery region. The utmost inner periphery pair has a difference between the second and the first impurity amounts, which is larger than a difference in the center region.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: January 8, 2008
    Assignee: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Tomoatsu Makino, Yoshiyuki Hattori, Kyoko Okada
  • Publication number: 20080001261
    Abstract: In order to suppress deterioration in charge balance and maintain excellent withstand voltage characteristics after forming a super junction structure on a semiconductor substrate, a plurality of columnar first epitaxial layers are respectively formed on a surface of a substrate main body at predetermined intervals, and a plurality of second epitaxial layers are respectively formed in trenches between the plurality of first epitaxial layers. A concentration distribution of a dopant included in the first epitaxial layer in a surface parallel with the surface of the substrate main body is configured to match with a concentration distribution of a dopant included in the second epitaxial layer in a surface parallel with the surface of the substrate main body.
    Type: Application
    Filed: August 30, 2007
    Publication date: January 3, 2008
    Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Hitoshi Yamaguchi
  • Publication number: 20070145479
    Abstract: A semiconductor device includes: two main electrodes; multiple first regions; and multiple second regions. The first region having a first impurity concentration and a first width and the second region having a second impurity concentration and a second width are alternately repeated. A product of the first impurity concentration and the first width is equal to a product of the second impurity concentration and the second width. The first width is equal to or smaller than 4.5 ?m. The first impurity concentration is lower than a predetermined concentration satisfying a RESURF condition. A ratio between on-state resistances of the device at 27° C. and at 150° C. is smaller than 1.8.
    Type: Application
    Filed: December 27, 2006
    Publication date: June 28, 2007
    Applicant: DENSO CORPORATION
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Yoshiyuki Hattori, Kyoko Okada
  • Publication number: 20070120201
    Abstract: A semiconductor device having a super junction MOS transistor includes: a semiconductor substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; a channel forming region on a first surface portion of the second semiconductor layer; a source region on a first surface portion of the channel forming region; a source contact region on a second surface portion of the channel forming region; a gate electrode on a third surface portion of the channel forming region; a source electrode on the source region and the source contact region; a drain electrode on a backside of the substrate; and an anode electrode on a second surface portion of the second semiconductor layer. The anode electrode provides a Schottky barrier diode.
    Type: Application
    Filed: November 14, 2006
    Publication date: May 31, 2007
    Applicant: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Jun Sakakibara
  • Publication number: 20070108444
    Abstract: In order to suppress deterioration in charge balance and maintain excellent withstand voltage characteristics after forming a super junction structure on a semiconductor substrate, a plurality of columnar first epitaxial layers are respectively formed on a surface of a substrate main body at predetermined intervals, and a plurality of second epitaxial layers are respectively formed in trenches between the plurality of first epitaxial layers. A concentration distribution of a dopant included in the first epitaxial layer in a surface parallel with the surface of the substrate main body is configured to match with a concentration distribution of a dopant included in the second epitaxial layer in a surface parallel with the surface of the substrate main body.
    Type: Application
    Filed: May 17, 2006
    Publication date: May 17, 2007
    Inventors: Syouji Nogami, Tomonori Yamaoka, Shoichi Yamauchi, Hitoshi Yamaguchi
  • Publication number: 20070082455
    Abstract: Closure at the opening of a trench with an epitaxial film is restrained, and thereby, filling morphology in the trenches is improved. A method for manufacturing a semiconductor substrate includes a step for growing an epitaxial layer 11 on the surface of a silicon substrate 13, a step of forming a trench 14 in this epitaxial layer, and a step of filling the inside of the trench 14 with the epitaxial film 12, wherein mixed gas made by mixing halogenoid gas into silicon source gas is circulated as material gas in filling the inside of the trench with the epitaxial film, and when the standard flow rate of the halogenoid gas is defined as Xslm and the film formation speed of the epitaxial film formed by the circulation of the silicon source gas is defined as Y?m/min, in the case when the aspect ratio of the trench is less than 10, an expression Y<0.2X+0.10 is satisfied, and in the case that the aspect ratio of the trench is between 10 and less than 20, an expression Y<0.2X+0.
    Type: Application
    Filed: October 6, 2006
    Publication date: April 12, 2007
    Inventors: Syouji NOGAMI, Tomonori Yamaoka, Shoichi Yamauchi, Hitoshi Yamaguchi, Takumi Shibata
  • Publication number: 20070032092
    Abstract: A method for manufacturing a semiconductor device includes steps of: forming a trench on a semiconductor substrate, which is made of silicon; and filling the trench with an epitaxial layer. The epitaxial layer is made of silicon, and the step of filling the trench includes a step of performing a plasma CVD method with using a silicon source gas. By using anisotropic character of a plasma, the epitaxial layer is selectively deposited on a bottom of the trench. Thus, the trench is filled with the epitaxial layer having no void.
    Type: Application
    Filed: August 1, 2006
    Publication date: February 8, 2007
    Applicant: DENSO CORPORATION
    Inventors: Takumi Shibata, Shoichi Yamauchi, Hitoshi Yamaguchi, Masaru Hori
  • Patent number: 7170119
    Abstract: In a vertical type MOSFET device having a super junction structure, in which a N conductive type column region and a P conductive type column region are alternately aligned, regarding to a distance between a terminal end of an active region and a terminal end of a column region, the terminal end of the column region is disposed at a position, which is separated from the active region terminal end by a distance obtained by subtracting a half of a width of the N conductive type column region from a distance corresponding to a depth of the column region. Thus, an electric field concentration at a specific portion in a region facing a narrow side of the column structure is prevented so that a breakdown voltage of the vertical type MOSFET is improved.
    Type: Grant
    Filed: August 20, 2004
    Date of Patent: January 30, 2007
    Assignee: Denso Corporation
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Takashi Suzuki, Kyoko Nakashima
  • Publication number: 20060286751
    Abstract: A semiconductor device includes: a semiconductor substrate; an element region having a semiconductor element including an impurity layer and a trench, wherein the impurity layer is disposed in the trench, and wherein the trench is disposed on a main surface of the substrate; and a field region disposed around the element region. The trench is an aggregation of a plurality of stripe line trenches so that the element region has a polygonal shape. The field region includes a dummy trench disposed along with one side of the polygonal shape on a periphery of the element region. The dummy trench has a width and a longitudinal direction, which are equal to those of the trench. The field region further includes an impurity layer disposed in the dummy trench.
    Type: Application
    Filed: May 25, 2006
    Publication date: December 21, 2006
    Applicant: DENSO CORPORATION
    Inventors: Yasushi Urakami, Jun Sakakibara, Hitoshi Yamaguchi
  • Publication number: 20060275980
    Abstract: A semiconductor device includes: a semiconductor substrate having a first surface and a second surface, wherein the substrate has a first conductive type; a first trench extending from the first surface of the semiconductor substrate in a depth direction; and an epitaxial semiconductor layer having a second conductive type, wherein the epitaxial semiconductor layer is disposed in the first trench. The first trench includes an inner wall as an interface between the semiconductor substrate and the epitaxial semiconductor layer so that the interface provides a PN junction. The first trench has an aspect ratio equal to or larger than 1.
    Type: Application
    Filed: May 16, 2006
    Publication date: December 7, 2006
    Applicant: DENSO CORPORATION
    Inventors: Jun Sakakibara, Hitoshi Yamaguchi, Naohiro Suzuki
  • Publication number: 20060255411
    Abstract: A semiconductor device includes: a MOS transistor; a protection diode; and a semiconductor substrate. The MOS transistor and the protection diode are disposed in the semiconductor substrate. The drain of the MOS transistor is connected to the cathode of the protection diode. The source of the MOS transistor is connected to the anode of the protection diode. The MOS transistor has a withstand voltage defined as VT. The protection diode has a withstand voltage defined as VD, a parasitic resistance defined as RD, and a maximum current defined as IRmax. They satisfy a relationship of VT>VD+IRmax×RD. The maximum current of IRmax is equal to or larger than 45 Amperes.
    Type: Application
    Filed: May 2, 2006
    Publication date: November 16, 2006
    Applicant: DENSO CORPORATION
    Inventors: Naohiro Suzuki, Hitoshi Yamaguchi
  • Publication number: 20060218916
    Abstract: Provided is a driving motor controlling device of a construction machine, including a driving motor which is included in the construction machine having a swivel joint interposed between an upper body and a lower body, and is connected to a pump and a tank through the swivel joint, and a motor control valve which switches a state for connecting the pump and the tank to the driving motor such that the driving motor is controlled to a stop state, a normal rotation state, or a reverse rotation state, wherein the motor control valve has a neutral position for the stop state, a normal rotation position for the normal rotation state, and a reverse rotation position for the reverse rotation state, and is switched to the neutral position, the normal rotation position, or the reverse rotation position, based on a command from a control device manipulated by a operator and a pressure of an inflow side of hydraulic oil into the driving motor, wherein the motor control valve is disposed in the lower body in which the dri
    Type: Application
    Filed: March 29, 2006
    Publication date: October 5, 2006
    Applicant: Nabtesco Corporation
    Inventors: Teruhisa Ando, Nobuaki Shimizu, Masahiro Tsunemi, Hitoshi Yamaguchi
  • Patent number: 7112519
    Abstract: A semiconductor device includes: an n+ type drain region; an n type drift region that connects with the n+ type drain region; a p type body region; a n+ type source region that connects with the p type body region; and a gate electrode that is provided, with being covered by a gate insulation film, in a gate trench that penetrates the p type body region. The semiconductor further includes: a p type silicon region that adjoins the n type drift region; and an n type silicon region provided in a region almost including a carrier passage that connects the n type drift region and the p type body region. Here, the p type silicon region and the p type body region directly connect with each other.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: September 26, 2006
    Assignee: Denso Corporation
    Inventors: Hitoshi Yamaguchi, Yoshiyuki Hattori
  • Publication number: 20060170037
    Abstract: In a vertical type MOSFET device having a super junction structure, in which a N conductive type column region (2) and a P conductive type column region (3) are alternately aligned, regarding to a distance between a terminal end (17) of an active region (13) and a terminal end (16) of a column region (4), the terminal end (16) of the column region (4) is disposed at a position, which is separated from the active region terminal end (17) by a distance obtained by subtracting a half of a width of the N conductive type column region (2) from a distance corresponding to a depth of the column region (4). Thus, an electric field concentration at a specific portion in a region facing a narrow side of the column structure is prevented so that a breakdown voltage of the vertical type MOSFET is improved.
    Type: Application
    Filed: August 20, 2004
    Publication date: August 3, 2006
    Inventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Takashi Suzuki, Kyoko Nakashima
  • Publication number: 20060138407
    Abstract: A semiconductor device includes a body region, a drift region having a first part and a second part, and a trench gate electrode. The body region is disposed on the drift region. The first and second parts extend in an extending direction so that the second part is adjacent to the first part. The trench gate electrode penetrates the body region and reaches the drift region so that the trench gate electrode faces the body region and the drift region through an insulation layer. The trench gate electrode extends in a direction crossing with the extending direction of the first and second parts. The first part includes a portion near the trench gate electrode, which has an impurity concentration equal to or lower than that of the body region.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Applicant: DENSO CORPORATION
    Inventors: Hitoshi Yamaguchi, Mikimasa Suzuki, Yoslhiyuki Hattori
  • Patent number: 7063751
    Abstract: A trench is formed in a semiconductor substrate through a mask composed of a silicon oxide film formed on the semiconductor substrate. Then, an edge portion at an opening portion of the mask is etched so that the width of the mask opening width is greater than the width of the trench. After that, the inner surface of the trench is smoothed by thermal treatment around at 1000° C. in non-oxidizing or non-nitriding atmosphere under low pressure. Then, the trench is filled with an epitaxial film. After that, the epitaxial film is polished to complete the substrate.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: June 20, 2006
    Assignee: Denso Corporation
    Inventors: Yasushi Urakami, Shoichi Yamauchi, Hitoshi Yamaguchi, Nobuhiro Tsuji