Abstract: The present invention relates to a brushless motor, and more particularly, to a brushless motor capable of cogging torque and torque ripples of the motor by means of design structures such as a shape of an opposing surface of a pole shoe, a shape of an outer circumferential surface of a rotor, and shapes and arrangement of permanent magnets.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: An embodiment multi-way coolant valve includes an outer housing including first to third outer inlets, first to third outer outlets, and a pump mount portion coupled to one of the outer outlets, an inner housing rotatably provided within the outer housing and including penetration holes corresponding to the outer inlets and outlets, a coolant line defined by a selective connection of the penetration holes such that the outer inlets and outlets are selectively connected, pads interposed between an interior circumference of the outer housing and an exterior circumference of the inner housing at locations of the outer inlets and outlets, respectively, and a driving device connected to a rotation center of the inner housing to selectively rotate the inner housing within the outer housing, wherein the inner housing is configured to rotate by a preset interval according to a selected vehicle mode.

Abstract: An inverter module according to an embodiment of the present invention comprises: a high voltage circuit unit which generates an inverter control voltage and a motor driving voltage by using a first DC voltage; a high voltage circuit pattern which electrically connects the high voltage circuit unit; a low voltage circuit unit which communicates with an external device by using a second DC voltage having a smaller magnitude than the first DC voltage; and a low voltage circuit pattern which electrically connects the low voltage circuit unit. The high voltage circuit pattern and the low voltage circuit pattern are spaced apart from each other.

Abstract: A pad liner includes a first pad clip that surrounds and is coupled to a side protrusion protruding in a lateral direction from a brake pad, and a torque support located under the first pad clip and between a side surface of the brake pad and the caliper body. The torque support supports a braking torque. The first pad clip includes a reference surface located on one of a top surface and a bottom surface of the side protrusion, a vertical elastic portion located on an opposite side from the reference surface that pressurizes the side protrusion in a direction of the reference surface, and a clip side portion that connects the reference surface and the vertical elastic portion and surrounds a side surface of the side protrusion. The pad liner minimizes a vertical gap and movement of the brake pad.

Abstract: Disclosed is a method of identifying dementia by at least one processor of a device. The method includes performing a first task that causes a first object to be displayed on a first region of a screen displayed on a user terminal; and when a preset condition is satisfied, performing a second task that causes at least one object, which induces the user's gaze, to be displayed instead of the first object on the screen of the user terminal.

Abstract: A manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a first seed layer in the opening; forming a first buffer layer by surface-treating the first seed layer; and forming a blocking layer by oxidizing the first seed layer through the first buffer layer.

Abstract: An insulin patch control method and a device therefor are provided. An insulin patch control method and a device therefor are provided. The insulin patch control method according to one embodiment of the present invention comprises the steps of: obtaining, from an insulin patch, blood glucose information measured by a blood glucose sensor; inputting the obtained blood glucose information into a first neural network; estimating a pump parameter of the insulin patch on the basis of output data of the first neural network; and simulating the insulin patch by inputting the blood sugar information and the pump parameter into a second neural network.

Abstract: A lithium secondary battery includes a cathode including a cathode current collector and a cathode active material layer formed on the cathode current collector, and an anode including an anode current collector and an anode active material layer formed on the anode current collector. The anode active material layer has an area larger than that of the cathode active material layer. The cathode active material layer includes a central portion and an outer portion surrounding the central portion, and the outer portion has a specific capacity less than that of the central portion.

Abstract: A storage device is disclosed. The storage device may comprise storage for input encoded data. A controller may process read requests and write requests from a host computer on the data in the storage. An in-storage compute controller may receive a predicate from the host computer to be applied to the input encoded data. A transcoder may include an index mapper to map an input dictionary to an output dictionary, with one entry in the input dictionary mapped to an entry in the output dictionary, and another entry in the input dictionary mapped to a “don't care” entry in the output dictionary.

Abstract: A method of identifying dementia is disclosed that includes causing a user terminal to display an N-th screen including a plurality of objects. The user terminal may further display an N+1-th screen with the objects rearranged at positions on the N+1-th screen which are different from positions of the objects included in the N-th screen when an N-th selection input of selecting any one from among the objects included in the N-th screen is received. When an N+1-th selection input for selecting any one from among the objects included in the N+1-th screen is received, a third task of determining whether an answer of the N+1-th selection input is correct is performed based on whether the object selected from the N+1-th selection input is the same as at least one object selected from at least one previous selection input including the N-th selection input.

Abstract: A semiconductor device may include a gate structure, a channel structure extending through the gate structure, a first hydrogen supply layer disposed on the gate structure, having a first hydrogen concentration, and comprising an oxygen vacancy, and a hydrogen blocking layer disposed on the first hydrogen supply layer and having a second hydrogen concentration lower than the first hydrogen concentration.

Abstract: Provided is a method of database management including locating, with a recovery logic, a first metadata table using a beginning metadata table key, reading, by the recovery logic, the first metadata table, retrieving, with the recovery logic, a first next metadata table key of the first metadata table, locating, by the recovery logic, a second metadata table based on the first next metadata table key or based on a third next metadata table key of a third metadata table having a third metadata table range between a first metadata table range of the first metadata table and a second metadata table range of the second metadata table, reading, by the recovery logic, the second metadata table, determining, by the recovery logic, the second metadata table lacks valid keys in the second metadata table range, and making available, by the recovery logic, memory space associated with the second metadata table.

Abstract: The present invention relates to a method of manufacturing polycrystalline silicon ingot using a crucible in which an oxygen exhaust passage is formed by single crystal or polycrystalline rods, the method including the steps of: manufacturing the single crystal or polycrystalline silicon rods each having the shape of a quadrilateral pillar; putting the single crystal or polycrystalline quadrilateral pillar-shaped silicon rods into the crucible in such a manner as to be arranged close to one another along the inner peripheral surface of the crucible to thus form a space portion inside the single crystal or polycrystalline silicon rods, into which silicon chunks are put, and the oxygen exhaust passages between the inner peripheral surface of the crucible and the respective surfaces of the single crystal or polycrystalline silicon rods oriented toward the inner peripheral surface of the crucible; putting the silicon chunks into the space portion of the crucible; and melting and crystallizing the silicon chunks.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.

Abstract: A semiconductor device including a first source layer including a first part having a first grain size and a second part having a second grain size smaller than the first grain size, a gate structure on the first source layer, and a channel structure passing through the gate structure and the second part of the first source layer.

Abstract: A storage device is disclosed. The storage device may comprise storage for input encoded data. A controller may process read requests and write requests from a host computer on the data in the storage. An in-storage compute controller may receive a predicate from the host computer to be applied to the input encoded data. A transcoder may include an index mapper to map an input dictionary to an output dictionary, with one entry in the input dictionary mapped to an entry in the output dictionary, and another entry in the input dictionary mapped to a “don't care” entry in the output dictionary.

Abstract: Disclosed is a semiconductor device including a gate structure located on a source structure, and including conductive layers and insulating layers that are alternately stacked on each other, a contact plug passing through the gate structure, and electrically connected to the source structure, a stressor surrounding sidewalls of the contact plug, and a seed layer surrounding the stressor.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.