Abstract: Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

Abstract: The present invention may provide a motor comprising an inverter housing in which a substrate is disposed, a connector which is mounted on the inverter housing and electrically connects the substrate and a cable and wherein the connector includes a body and a first terminal coupled to the body, one side of the first terminal is in electrical contact with the substrate, the other side of the first terminal is in contact with the cable, wherein the inverter housing includes a connector mounting portion which accommodate the body of the connector, sealing members seal a gap between the connector mounting portion and the connector.

Abstract: Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: A substrate processing apparatus includes: a disk including a plurality of electrostatic chucks periodically disposed at a constant radius from a central axis; a disk support supporting the disk; a DC line electrically connected to the plurality of electrostatic chucks through the disk support; and a power supply configured to supply power to the DC line. The DC line includes: a first DC line penetrating through the disk support from the power supply; a power distribution unit configured to distribute the first DC line to connect the first DC line to each of the plurality of electrostatic chucks; and a plurality of second DC lines respectively connected to the plurality of electrostatic chucks in the power distribution unit.

Abstract: Provided is a method of data storage, the method including receiving a write request including a user key, determining the user key exists in a cache, generating or updating metadata corresponding to the user key, writing data corresponding to the write request to a storage device, converting the metadata to a device format corresponding to the storage device, and storing the metadata on the storage device.

Abstract: Provided is a method of data storage, the method including identifying a plurality of transactions in a pending queue, the transactions having one or more key value updates respectively corresponding to a plurality of keys, identifying a commonly associated key of the plurality of keys associated with commonly associated key value updates of the key value updates belonging to different ones of the transactions, respectively assigning transaction group IDs to the transactions based on respective transaction IDs assigned to the transaction group IDs, grouping the transactions into a respective transaction group of a plurality of transaction groups based on the assigned transaction group ID, and merging conflicting data writes corresponding to the commonly associated key value updates of the commonly associated key for grouped transactions of the transactions that are in a same one of the transaction groups.

Abstract: A vertical semiconductor device and a method for fabricating the same may include forming an alternating stack of dielectric layers and sacrificial layers over a lower structure, forming an opening by etching the alternating stack, forming a non-conformal blocking layer on the alternating stack in which the opening is formed, adsorbing a deposition inhibitor on a surface of the blocking layer to convert the non-conformal blocking layer into a conformal blocking layer on which the deposition inhibitor is adsorbed, and forming a charge storage layer on the conformal blocking layer.

Abstract: Disclosed is a semiconductor device with improved electrical characteristics and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked on a substrate, forming a first through portion in the alternating stack, etching first portions of the sacrificial layers through the first through portion, to form lateral recesses between the dielectric layers, forming charge trapping layers isolated in the lateral recesses, forming a second through portion by etching the alternating stack in which second portions of the sacrificial layers remain, removing the second portions of the sacrificial layers through the second through portion, to form gate recesses that expose non-flat surfaces of the charge trapping layers, flattening the non-flat surfaces of the charge trapping layers, and forming a gate electrode that fills the gate recesses.

Abstract: The present invention relates to a brushless motor, and an objective of the present invention is to provide a brushless motor which can significantly reduce the cogging torque and torque ripple of the motor by minimizing the rate of change of magnetoresistance in accordance with a change in position of a rotor through the optimization of the shape design of the rotor and a stator, and can also reduce the weight of the brushless motor through the optimization of the shape design taking into consideration the materials of the rotor and the stator.

Abstract: Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

Abstract: An analog front-end receiver including a termination resistor configured to receive first and second differential signals from different data lines, the second differential signal being differential with respect to the first differential signal, an active equalizer configured to receive a first input differential signal through a first input node and a second input differential signal through a second input node, the first and second input differential signals both having an input common mode voltage, the first and second input differential signals being based on the first and second differential signal, respectively, and output first and output differential signals to first and second output nodes, respectfully, the second output differential signal being differential with respect to the first output differential signal, and an input common mode voltage generator configured to adjust the input common mode voltage to be equal to an output common mode voltage of the first output differential signal.

Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers, which are alternately stacked; an opening including a first opening penetrating the stack structure and second openings protruding from the first opening; and a channel layer including channel regions located in the second openings and impurity regions located in the first opening, the impurity regions having an impurity concentration higher than that of the channel regions.

Abstract: Provided is an analog front-end receiver including: a first equalizer including a first block switch configured to receive a first differential signal through a first node, and configured to block the first differential signal in a first operation mode; a second equalizer including a second block switch configured to receive a second differential signal through a second node, and configured to block the second differential signal in the first operation mode; a terminating resistor provided between the first node and the second node, and configured to receive the first differential signal via the first node, and receive the second differential signal via the second node; and a low pass filter configured to receive a third differential signal converted by the terminating resistor from the first differential signal, and configured to receive a fourth differential signal converted by the terminating resistor from the second differential signal.

Abstract: A semiconductor memory device includes: a tunnel insulating layer disposed between a conductive pattern and a channel layer; a data storage layer disposed between the conductive pattern and the tunnel insulating layer, the data storage layer including a silicon nitride layer; a first blocking insulating layer disposed between the conductive pattern and the data storage layer; a second blocking insulating layer disposed between the conductive pattern and the first blocking insulating layer; and a carbon containing layer disposed at at least one position among a position between the tunnel insulating layer and the data storage layer, a position between the first blocking insulating layer and the data storage layer, a position in the tunnel insulating layer, and a position between the first blocking insulating layer and the second blocking insulating layer.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.

Abstract: A storage device is disclosed. The storage device may comprise storage for input encoded data. A controller may process read requests and write requests from a host computer on the data in the storage. An in-storage compute controller may receive a predicate from the host computer to be applied to the input encoded data. A transcoder may include an index mapper to map an input dictionary to an output dictionary, with one entry in the input dictionary mapped to an entry in the output dictionary, and another entry in the input dictionary mapped to a “don't care” entry in the output dictionary.

Abstract: A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.

Abstract: The present invention relates to a composition for preventing or treating cellular senescence-associated diseases comprising homoharringtonine as an active ingredient, and it was confirmed that the composition comprising homoharringtonine as an active ingredient exhibits a senolytics effect of selectively killing aging-induced fibroblasts and renal tubular cells, whereas aging-induced vascular endothelial cells and epithelial melanocytes and retinal pigmented epithelial cells, and exhibits a senomorphics effect of restoring the function and morphology of cells, and thus the homoharringtonine acts differently depending on the type of cells to effectively prevent or treat senile eye disease, tissue fibrosis disease, atherosclerosis, osteoarthritis, degenerative brain disease, chronic skin damage, obesity and diabetes caused by cellular aging and can be provided as a composition for whitening skin and life extension.

Abstract: Disclosed is a memory device and a method for fabricating the same, and the method may include forming an alternating stack in which dielectric layers and sacrificial layers are alternately stacked over a substrate, each of the sacrificial layers being a combination of porous and non-porous materials, forming a vertical opening penetrating the alternating stack, converting exposed surfaces of the sacrificial layers located on a side wall of the vertical opening into blocking layers through an oxidation process, forming a vertical channel structure contacting the blocking layers in the vertical opening, and replacing non-converting portions of the sacrificial layers with conductive layers, wherein each of the conductive layers comprises a round-like edge contacting each of the blocking layers.