Abstract: An integrated circuit device such as an integrated circuit memory device, includes a first fuse group such as a first laser fuse group including a plurality of first laser fuses each having a first narrow end, a second opposite end which is wider and a bent central portion. Pitches of the first end of the plurality of first laser fuses are narrow and pitches of the second end are wide. The plurality of first laser fuses are adjacent one another. A second fuse group such as a second laser fuse group includes a plurality of second laser fuses each having a first wide end, a second opposite end which is narrower, and a bent central portion. Pitches of the first end of the plurality of second laser fuses are wide and pitches of the second end are narrow. The second plurality of laser fuses are adjacent one another. The first ends of the laser fuses in the first laser fuse group are adjacent the first ends of laser fuses in the second laser fuse group.

Abstract: Graphics memory devices include an output register having an input electrically coupled to an output signal line (DO) and first and second data output buffers responsive to first and second clock signals (CLK1, CLK2), respectively. The first data output buffer has an input electrically coupled to the output signal line (DO) and the second data output buffer has an input electrically coupled to an output of the output register. These memory devices also include at least one memory cell array and a read data driver that has an input electrically coupled to the memory cell array by an input/output signal line (I/O) and an output electrically coupled to the output signal line (DO). To provide improved performance for graphics processing applications, a clock signal generator is provided that generates the first and second clock signals at different frequencies and/or different phases relative to each other.

Abstract: A redundancy fuse box of a semiconductor memory device which minimizes address line loading by organizing fuse cells into fuse cell groups sharing the same sub-address line. The address signal therefore has to traverse across a shorter distance along the semiconductor device, which contributes to a reduction in cell line loading. The redundancy fuse box includes a plurality of fuse cells, each having a transistor and fuse, to which an address signal of a memory cell is applied. The respective fuse boxes are constructed as one fuse box by being laid out in the same place. The fuse box includes a plurality of fuse cells which receive the same address signal along a common sub-address line and is wired so that outputs of the fuse cells which received the same address signal contribute to different redundancy enable signals.

Abstract: The semiconductor memory device includes a clock signal generating circuit, a precharge circuit, a write circuit, and an input/output circuit. The clock signal generating circuit generates a second clock signal having a second state of a constant interval irrespective of a period of a first clock signal. The precharge circuit precharges a data input/output line in response to a precharge signal. The write circuit transfers, during a write operation, input data signal to the data input/output line each time the second clock signal is a first state under the state that a power signal and the precharge signal are the first state. The input/output circuit transfers data transmitted to the data input/output line to a cell.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: There is provided a semiconductor memory device which does not require an additional input pad to apply a signal for discriminating between a normal cell and a redundant cell. The semicodnuctor memory device has (claim 1). Therefore, the normal cell array or the redundant cell array is sequentially selected and tested by using the same input pad to which the bank select bit is input, without an additional pad.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A word line voltage boosting circuit varies a word line output voltage according to variation of the number of the word lines to be activated. A boosting circuit boosts a word line voltage which has been precharged to a first level voltage to a second level voltage in response to an activation signal. A voltage adding circuit further boosts the word line voltage to a third voltage level by adding a predetermined voltage to the second level voltage if the number of the word lines to be activated increases. A driving circuit includes a bootstrap circuit for stably providing the boosted word line voltage to an output line.

Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A data input/output sensing circuit of a semiconductor memory device including a plurality of memory cells, the circuit comprises: input/output lines of the memory cell; data input/output terminals connected to outside of the memory cells; a single data input/output line connected between the input/output lines and the data input/output terminals; a sensing unit for sensing whether or not effective data is provided in the data input/output lines to thereby generate a sensing signal; an output driving unit for transmitting data of the data input/output lines to the data input/output terminals in response to the sensing signal; and a writing driving unit for inputting data of the data input/output terminals in response to the sensing signal.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.

Abstract: A data output buffer is used for a synchronous semiconductor memory device carrying out a data read/write operation in synchronism with an externally supplied clock.

Abstract: An optical pick-up objective lens driving apparatus comprises a rectangular moving member mounted for movement relative to an iron-core member in rectilinear focusing and tracking directions, respectively. The moving member carries focusing and tracking coils, and a lens. Magnetic pieces are disposed at respective corners of the moving member in opposing spacial relationship to magnetic plates of the iron core member to create a restoring force which biases the moving member to a pre-set position. The lens is mounted over a center of weight of the moving member.