Patents by Inventor Ho-kyun An

Ho-kyun An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210122394
    Abstract: A system for providing a speed profile of a self-driving vehicle includes a vehicle driving information prediction device, and a speed profile generation device, wherein the vehicle driving prediction device includes a navigation unit configured to set information on a drive route and a target travel time, a 3D map information provision unit configured to search for gradient information of the drive route set by the navigation unit, and a vehicle driving information provision unit, and wherein the speed profile generation device includes a vehicle energy consumption calculation unit configured to calculate energy consumption at a current speed of the vehicle when the vehicle runs along the set drive route, and a speed profile calculation unit configured to calculate a distance-based target speed profile by executing a dynamic programming algorithm.
    Type: Application
    Filed: July 1, 2020
    Publication date: April 29, 2021
    Inventors: Hee Yun Lee, Jae Sung Bang, Ho Kyun Chun, Dae Ki Hong
  • Publication number: 20190384669
    Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 19, 2019
    Inventors: Ho Kyun AN, Dong Hyun IM
  • Patent number: 10403735
    Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho Kyun An, Dong Hyun Im
  • Patent number: 10134854
    Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Dong Min Kang, Yong-Hwan Kwon, Dong-Young Kim, Seong Il Kim, Hae Cheon Kim, Eun Soo Nam, Jae Won Do, Byoung-Gue Min, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho
  • Patent number: 9899226
    Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 20, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun Ahn, Hae Cheon Kim, Jong Won Lim, Dong Min Kang, Yong Hwan Kwon, Seong Il Kim, Zin Sig Kim, Eun Soo Nam, Byoung Gue Min, Hyung Sup Yoon, Kyung Ho Lee, Jong Min Lee, Kyu Jun Cho
  • Publication number: 20180019318
    Abstract: Forming a semiconductor device includes forming a first conductive line on a substrate, forming a memory cell including a switching device and a data storage element on the first conductive line, and forming a second conductive line on the memory cell. Forming the switching device includes forming a first semiconductor layer, forming a first doped region by injecting a n-type impurity into the first semiconductor layer, forming a second semiconductor layer thicker than the first semiconductor layer, on the first semiconductor layer having the first doped region, forming a second doped region by injecting a p-type impurity into an upper region of the second semiconductor layer, and forming a P-N diode by performing a heat treatment process to diffuse the n-type impurity and the p-type impurity in the first doped region and the second doped region to form a P-N junction of the P-N diode in the second semiconductor layer.
    Type: Application
    Filed: January 19, 2017
    Publication date: January 18, 2018
    Inventors: Ho Kyun AN, Dong Hyun IM
  • Patent number: 9837719
    Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the m
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: December 5, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong-Young Kim, Dong Min Kang, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Byoung-Gue Min, Ho Kyun Ahn, Hyung Sup Yoon, Sang-Heung Lee, Jong Min Lee, Jong-Won Lim, Yoo Jin Jang, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
  • Patent number: 9780176
    Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: October 3, 2017
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong Min Lee, Byoung-Gue Min, Hyung Sup Yoon, Dong Min Kang, Dong-Young Kim, Seong-Il Kim, Hae Cheon Kim, Jae Won Do, Ho Kyun Ahn, Sang-Heung Lee, Jong-Won Lim, Hyun Wook Jung, Kyu Jun Cho, Chull Won Ju
  • Publication number: 20170236909
    Abstract: A high electron mobility transistor includes a substrate including a first surface and a second surface facing each other and having a via hole passing through the first surface and the second surface, an active layer on the first surface, a cap layer on the active layer and including a gate recess region exposing a portion of the active layer, a source electrode and a drain electrode on one of the cap layer and the active layer, an insulating layer on the source electrode and the drain electrode and having on opening corresponding to the gate recess region to expose the gate recess region, a first field electrode on the insulating layer, a gate electrode electrically connected to the first field electrode on the insulating layer, and a second field electrode on the second surface and contacting the active layer through the via hole.
    Type: Application
    Filed: August 26, 2016
    Publication date: August 17, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun AHN, Dong Min KANG, Yong-Hwan KWON, Dong-Young KIM, SEONG IL KIM, Hae Cheon KIM, Eun Soo NAM, Jae Won DO, Byoung-Gue MIN, Hyung Sup YOON, Sang-Heung LEE, Jong Min LEE, Jong-Won LIM, Hyun Wook JUNG, Kyu Jun CHO
  • Publication number: 20170237171
    Abstract: Provided herein is a patch antenna including a multilayered substrate on which a plurality of dielectric layers are laminated; at least one metal pattern layer disposed between the plurality of dielectric layers outside a central area of the multilayered substrate; an antenna patch disposed on an upper surface of the multilayered substrate and within the central area; a ground layer disposed on a lower surface of the multilayered substrate; a plurality of connection via patterns penetrating the plurality of dielectric layers to connect the metal pattern layer and the ground layer, and surrounding the central area; a transmission line comprising a first transmission line unit disposed on the upper surface of the multilayered substrate and located outside the central area, and a second transmission line unit disposed on the upper surface of the multilayered substrate and located within the central area; and an impedance transformer located below the second transmission line unit within the central area of the m
    Type: Application
    Filed: August 5, 2016
    Publication date: August 17, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong-Young KIM, Dong Min KANG, SEONG-IL KIM, Hae Cheon KIM, Jae Won DO, Byoung-Gue MIN, Ho Kyun AHN, Hyung Sup YOON, Sang-Heung LEE, Jong Min LEE, Jong-Won LIM, Yoo Jin JANG, Hyun Wook JUNG, Kyu Jun CHO, Chull Won JU
  • Patent number: 9657658
    Abstract: A method for controlling an air control valve in a diesel hybrid vehicle includes an engine stop detection step for detecting whether a diesel engine is stopped and a vehicle speed is less than a predetermined speed, a first noise and vibration blockade step for controlling a throttle valve to be closed when the diesel engine is stopped and the vehicle speed is less than the predetermined speed, and a first throttle valve control step for closing and then opening again the throttle valve for a predetermined time.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: May 23, 2017
    Assignee: Hyundai Motor Company
    Inventors: Ho-Kyun Chun, Hwa-Yong Jang
  • Publication number: 20170133471
    Abstract: The present invention relates to a high reliability field effect power device and a manufacturing method thereof. A method of manufacturing a field effect power device includes sequentially forming a transfer layer, a buffer layer, a barrier layer and a passivation layer on a substrate, patterning the passivation layer by etching a first region of the passivation layer, and forming at least one electrode on the first region of the barrier layer exposed by patterning the passivation layer, wherein the first region is provided to form the at least one electrode, and the passivation layer may include a material having a wider bandgap than the barrier layer to prevent a trapping effect and a leakage current of the field effect power device.
    Type: Application
    Filed: August 16, 2016
    Publication date: May 11, 2017
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong Min LEE, Byoung-Gue MIN, Hyung Sup YOON, Dong Min KANG, Dong-Young KIM, SEONG-IL KIM, Hae Cheon KIM, Jae Won DO, Ho Kyun AHN, Sang-Heung LEE, Jong-Won LIM, Hyun Wook JUNG, Kyu Jun CHO, Chull Won JU
  • Patent number: 9537458
    Abstract: Provided herein is a feedback amplifier including an amplifier circuit configured to amplify an input signal input from an input terminal and output the amplified input signal to an output terminal; a feedback circuit configured to apply a feedback resistance value to a signal output to the output terminal, and to control a gain of the amplifier circuit by adjusting the input signal by a bias voltage applied with a feedback resistance value determined; a packet signal sensor configured to generate a fixed resistance control signal for controlling a fixed resistance value included in the feedback resistance value through a comparison between the output from the output terminal with a minimum signal level; and a fixed resistance controller configured to control the fixed resistance value included in the feedback resistance value in response to the fixed resistance control signal.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: January 3, 2017
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sang Heung Lee, Dong Min Kang, Seong Il Kim, Ho Kyun Ahn, Hyung Sup Yoon, Jong Won Lim, Chull Won Ju
  • Patent number: 9438199
    Abstract: Provided herein is a component package including a matching unit and a matching method thereof, the matching unit including: a substrate; a transmission line formed on the substrate, the transmission line being connected to a terminal of the component package; a bonding wire electrically connecting the transmission line and a central component; and a capacitor unit having a plurality of capacitors electrically connected with the transmission line by wiring connection, wherein an inductance of the matching unit is variable by adjusting a length of the bonding wire, and a capacitance of the matching unit is variable by increasing or reducing the number of capacitors electrically connected to the transmission line, of among the capacitors inside the capacitor unit, by extending or cutting off the wiring connection.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: September 6, 2016
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dong Min Kang, Seong Il Kim, Sang Heung Lee, Chull Won Ju, Ho Kyun Ahn, Hyung Sup Yoon, Jong Won Lim
  • Patent number: 9403530
    Abstract: An air flow sensor chip-heating control device and method of a diesel hybrid electric vehicle controls whether an air flow sensor installed in an engine intake system of the diesel hybrid electric vehicle performs a chip-heating operation. Particularly, the air flow sensor chip-heating control device performs a chip heating operation of the air flow sensor based on a result obtained by deciding a driving history of an engine when the vehicle enters into a hybrid mode during driving of the engine.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: August 2, 2016
    Assignee: Hyundai Motor Company
    Inventors: Hwa Yong Jang, Ho Kyun Chun
  • Publication number: 20160108831
    Abstract: A method for controlling an air control valve in a diesel hybrid vehicle includes an engine stop detection step for detecting whether a diesel engine is stopped and a vehicle speed is less than a predetermined speed, a first noise and vibration blockade step for controlling a throttle valve to be closed when the diesel engine is stopped and the vehicle speed is less than the predetermined speed, and a first throttle valve control step for closing and then opening again the throttle valve for a predetermined time.
    Type: Application
    Filed: May 20, 2015
    Publication date: April 21, 2016
    Inventors: Ho-Kyun Chun, Hwa-Yong Jang
  • Patent number: 9305928
    Abstract: Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: April 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youngkuk Kim, Ho-Kyun An, Jaehyun Yeo, Badro Im, HanJin Lim, Sungho Jang, Insang Jeon
  • Publication number: 20160068154
    Abstract: An air flow sensor chip-heating control device and method of a diesel hybrid electric vehicle controls whether an air flow sensor installed in an engine intake system of the diesel hybrid electric vehicle performs a chip-heating operation. Particularly, the air flow sensor chip-heating control device performs a chip heating operation of the air flow sensor based on a result obtained by deciding a driving history of an engine when the vehicle enters into a hybrid mode during driving of the engine.
    Type: Application
    Filed: December 9, 2014
    Publication date: March 10, 2016
    Inventors: Hwa Yong Jang, Ho Kyun Chun
  • Publication number: 20150380482
    Abstract: Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
    Type: Application
    Filed: March 13, 2015
    Publication date: December 31, 2015
    Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Ho Kyun AHN, Hae Cheon KIM, Jong Won LIM, Dong Min KANG, Yong Hwan KWON, SEONG IL KIM, Zin Sig KIM, Eun Soo NAM, Byoung Gue MIN, Hyung Sup YOON, Kyung Ho LEE, Jong Min LEE, Kyu Jun CHO
  • Patent number: 9209266
    Abstract: Disclosed is a manufacturing method of a high electron mobility transistor. The method includes: forming a source electrode and a drain electrode on a substrate; forming a first insulating film having a first opening on an entire surface of the substrate, the first opening exposing a part of the substrate; forming a second insulating film having a second opening within the first opening, the second opening exposing a part of the substrate; forming a third insulating film having a third opening within the second opening, the third opening exposing a part of the substrate; etching a part of the first insulating film, the second insulating film and the third insulating film so as to expose the source electrode and the drain electrode; and forming a T-gate electrode on a support structure including the first insulating film, the second insulating film and the third insulating film.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: December 8, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Jong-Won Lim, Ho Kyun Ahn, Young Rak Park, Dong Min Kang, Woo Jin Chang, Seong-il Kim, Sung Bum Bae, Sang-Heung Lee, Hyung Sup Yoon, Chull Won Ju, Jae Kyoung Mun, Eun Soo Nam